Method for fabricating a power semiconductor package including vertically stacked driver IC
US-9299690-B2 · Mar 29, 2016 · US
Power semiconductor package having vertically stacked driver IC
US9502395B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9502395-B2 |
| Application number | US-201514876709-A |
| Country | US |
| Kind code | B2 |
| Filing date | Oct 6, 2015 |
| Priority date | Oct 18, 2012 |
| Publication date | Nov 22, 2016 |
| Grant date | Nov 22, 2016 |
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- Title
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- Abstract
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Abstract
Official abstract text for this publication.
In one implementation, a semiconductor package includes a control conductive carrier having a die side and an opposite input/output (I/O) side connecting the semiconductor package to a mounting surface. The semiconductor package also includes a control FET of a power converter switching stage attached to the die side of the control conductive carrier, and a driver integrated circuit (IC) for driving the control FET. The driver IC is situated above the control FET and is electrically coupled to the control FET by at least one conductive buildup layer formed over the control conductive carrier.
First claim
Opening claim text (preview).
The invention claimed is: 1. A semiconductor package comprising: a control carrier having a die side and an opposite input/output (I/O) side; a control FET attached to said die side of said control carrier; a driver integrated circuit (IC) for driving said control FET, said driver IC situated over said control FET and electrically coupled to said control FET by at least one conductive buildup layer. 2. The semiconductor package of claim 1 , further comprising: a sync carrier having another die side and another opposite input/output (I/O) side; a sync FET attached to said another die side of said sync carrier. 3. The semiconductor package of claim 1 , wherein said driver IC is electrically coupled to said at least one conductive buildup layer formed over said control carrier by bondwire. 4. The semiconductor package of claim 1 , wherein said driver IC is flip chip mounted over said at least one conductive buildup layer. 5. The semiconductor package of claim 1 , wherein said control FET comprises a silicon FET. 6. The semiconductor package of claim 1 , wherein said control FET comprises a III-Nitride FET. 7. A semiconductor package comprising: a sync carrier having a die side and an opposite input/output (I/O) side; a sync FET attached to said die side of said sync carrier; a driver integrated circuit (IC) for driving said sync PET, said driver IC situated over said sync FET and electrically coupled to said sync FET by at least one conductive buildup layer. 8. The semiconductor package of claim 7 , further comprising: a control carrier having another die side and another opposite input/output (I/O); a control FET attached to said another die side of said control carrier. 9. The semiconductor package of claim 7 , wherein said driver IC is electrically coupled to said at least one conductive buildup layer formed over said sync carrier by bondwire. 10. The semiconductor package of claim 7 , wherein said driver IC is flip chip mounted over said at least one conductive buildup layer. 11. The semiconductor package of claim 7 , wherein said sync FET comprises a silicon FET. 12. The semiconductor package of claim 7 , wherein said sync FET comprises a III-Nitride FET.
Assignees
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Classifications
between a chip and a stacked insulating package substrate, interposer or RDL · CPC title
between stacked chips · CPC title
between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title
between a chip and a stacked insulating package substrate, interposer or RDL · CPC title
between a chip and a stacked insulating package substrate, interposer or RDL · CPC title
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Frequently asked questions
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- What does patent US9502395B2 cover?
- In one implementation, a semiconductor package includes a control conductive carrier having a die side and an opposite input/output (I/O) side connecting the semiconductor package to a mounting surface. The semiconductor package also includes a control FET of a power converter switching stage attached to the die side of the control conductive carrier, and a driver integrated circuit (IC) for dr…
- Who is the assignee on this patent?
- Infineon Technologies Americas Corp
- What technology area does this patent fall under?
- Primary CPC classification H10W70/041. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Nov 22 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 2 related publications on this page (citations in our corpus or others sharing the same primary CPC).