Modulation circuit and modulation method with digital ELD compensation

Patent metadata

Field	Value
Publication number	US-9490835-B2
Application number	US-201514603590-A
Country	US
Kind code	B2
Filing date	Jan 23, 2015
Priority date	Jun 10, 2014
Publication date	Nov 8, 2016
Grant date	Nov 8, 2016

Abstract

A modulation circuit includes a digital quantizer and a compensation circuit. The digital quantizer is utilized to receive and truncate a digital quantizing input signal for generating a digital quantizing output signal. The compensation circuit compensates for a time delay of the modulation circuit and generates a compensation output signal. The digital quantizing input signal is generated by subtracting the compensation output signal from a digital integration output signal to compensate for the time delay before truncating the digital quantizing input signal.

First claim

What is claimed is:

1. A modulation circuit, comprising:
an analog stage, comprising:
an analog quantizer, utilized to sample and quantize an analog signal for generating a digital input signal; and
a digital stage, comprising:
a digital quantizer, utilized to receive and truncate a digital quantizing input signal according to the digital input signal for generating a digital quantizing output signal; and
a compensation circuit, coupled to the digital quantizer, utilized to compensate for a time delay of the modulation circuit and generate a compensation output signal, wherein the digital quantizing input signal is generated by subtracting the compensation output signal from a digital integration output signal to compensate for the time delay, the time delay comprising a time that the analog quantizer samples and quantizes the analog signal and a time that the digital quantizing output signal is fed back to the analog stage, wherein the compensation circuit comprises a flip flop and a digital multiplier.

2. The modulation circuit as claimed in claim 1 , wherein the modulation circuit further comprises a digital integrator to receive the digital input signal and generate the digital integration output signal.

3. The modulation circuit as claimed in claim 2 , wherein the modulation circuit further comprises a first adder coupled between the digital integrator and the digital quantizer, utilized to subtract the compensation output signal from the digital integration output signal for outputting the digital quantizing input signal.

4. The modulation circuit as claimed in claim 1 , wherein the modulation circuit further comprises a digital-to-analog converter to convert the output signal and generate an analog output signal, and the compensation circuit is arranged between the digital quantizer and the digital-to-analog converter.

5. The modulation circuit as claimed in claim 4 , wherein the modulation circuit further comprises a third adder to subtract the analog output signal from an input signal for generating an analog input signal.

6. The modulation circuit as claimed in claim 5 , wherein the modulation circuit further comprises an analog integrator coupled to the third adder to receive and integrate the analog input signal for generating an analog quantizing input signal.

7. The modulation circuit as claimed in claim 6 , wherein the analog quantizer is coupled to the analog integrator for converting the analog quantizing input signal into a digital conversion signal.

8. The modulation circuit as claimed in claim 7 , wherein the compensation circuit, the digital-to-analog converter and the analog quantizer are triggered by a clock signal.

9. A modulation circuit, comprising:
a shared analog quantizer configured for dual-channel operations, the shared analog quantizer receiving a first input signal for generating a first digital input signal and receiving a second input signal for generating a second digital input signal, wherein the first input signal and the second input signal are generated in different channels; and
a processing circuit, coupled to the analog quantizer for compensating a time delay of the modulation circuit, and truncating the first digital input signal to generate a first truncation signal after the time delay is compensated for, and truncating the second digital input signal to generate a second truncation signal after the time delay is compensated for, the truncation of the first and second digital inputs signals corresponding to reducing a respective bit width.

10. The modulation circuit as claimed in claim 9 , wherein the processing circuit further comprises:
a first digital processing circuit, utilized for compensating the time delay and truncating the first digital input signal to generate a first truncation signal after the time delay is compensate for; and
a second digital processing circuit, utilized for compensating the time delay and truncating the second digital input signal to generate a second truncation signal after the time delay is compensate for.

11. The modulation circuit as claimed in claim 9 , wherein the analog quantizer is input by a first clock signal and a second clock signal different from the first clock signal to alternatively quantize the first input signal and the second input signal.

12. The modulation circuit as claimed in claim 11 , wherein the modulation circuit further comprises a first digital-to-analog converter and a second digital-to-analog converter, the first digital-to-analog circuit is coupled to the analog quantizer and input by the first clock signal to convert the first truncation signal, and the second digital-to-analog circuit is coupled to the analog quantizer and input by the second clock signal to convert the second truncation signal.

13. The modulation circuit as claimed in claim 12 , the modulation circuit further comprises a first dynamic match circuit and a second dynamic match circuit, the first dynamic match circuit is coupled between the first digital-to-analog converter and the first digital processing circuit to improve linearity of the first truncation signal, and the second dynamic match circuit is coupled between the second digital-to-analog converter and the second digital processing circuit to improve linearity of the second truncation signal.

14. A modulation method utilized for a modulation circuit, comprising:
compensating, by a compensation circuit, a time delay of the modulation circuit by receiving an output signal and generating a compensation output signal, the time delay corresponding to analog quantization time of an analog stage and feedback time of the output signal to the analog stage;
generating a digital quantizing input signal by subtracting the compensation output signal from a digital integration output signal;
truncating and quantizing the digital quantizing input signal to generate a digital quantizing output signal, wherein compensating the time delay is executed before truncating and quantizing the digital quantizing input signal; and
adding a truncation noise to the digital quantizing output signal to generate the output signal input to the compensation circuit.

15. The modulation method as claimed in claim 14 , further comprising:
converting the output signal to generate an analog output signal.

16. The modulation method as claimed in claim 15 , further comprising:
subtracting the analog output signal from an input signal to generate an analog input signal; and
integrating the analog input signal to generate an analog quantizing input signal.

17. The modulation method as claimed in claim 16 , further comprising:
converting the analog quantizing input signal into a digital conversion signal; and
adding a quantization noise to the digital conversion signal to generate a digital input signal.

18. The modulation method as claimed in claim 17 , further comprising receiving and integrating the digital input signal to generate the digital integration output signal.

Assignees

• Mediatek Inc

Inventors

• Wang Tze-Chien

Classifications

• H03M3/37 Primary

  Compensation or reduction of delay or phase error · CPC title

• H03M3/458

  Analogue/digital converters using delta-sigma modulation as an intermediate step · CPC title