Vertical floating body storage transistors formed in bulk devices and having buried sense and word lines

Patent metadata

Field	Value
Publication number	US-9484457-B2
Application number	US-201213404759-A
Country	US
Kind code	B2
Filing date	Feb 24, 2012
Priority date	Feb 25, 2011
Publication date	Nov 1, 2016
Grant date	Nov 1, 2016

Abstract

A semiconductor device comprises a memory area including floating body transistors in the form of pillar structures, which are formed in a bulk architecture. The pillar structures may be appropriately addressed on the basis of a buried word line and a buried sense region or sense lines in combination with an appropriate bit line contact regime.

First claim

What is claimed:

1. A method, comprising:
forming a stack of doped semiconductor layers above a doped semiconductor region of a first conductivity type, said stack comprising a top layer of said first conductivity type and a bottom layer of a second conductivity type, said bottom layer forming a PN junction with said doped semiconductor region;
forming first trench isolation regions in said stack of doped semiconductor layers;
forming combined word lines in said stack of doped semiconductor layers and said first trench isolation regions, said combined word lines extending substantially transversely to said first trench isolation regions;
forming second trench isolation regions in said stack of doped semiconductor layers, said second trench isolation regions extending substantially transversely to said first trench isolation regions and laterally delineating, in combination with said first trench isolation regions and said combined word lines, a plurality of pillar structures comprising said top and bottom layers;
forming a word line trench isolation region in each of said combined word lines so as to form a first split word line and a second split word line from each of said combined word lines, said word line trench isolation region including an excess material portion extending above said top layer;
forming spacers on said excess material portion;
etching said plurality of pillar structures using said spacers and said excess material portion as an etch mask to form trenches in said plurality of pillar structures;
filling said trenches with an insulating material to form third isolation trenches extending substantially parallel to said first trench isolation regions and further delineate said plurality of pillar structures; and
removing said excess material portion and said spacers.

2. The method of claim 1 , further comprising forming a bit line contact region on each of said plurality of pillar structures by exposing a portion of said bottom layer and forming a bit line thereon.

3. The method of claim 1 , wherein forming said combined word line comprises forming word line trenches in said stack of doped semiconductor layers and in said first trench isolation regions, forming a dielectric liner on exposed surface areas of said word line trenches and forming a conductive material on said dielectric liner.

4. The method of claim 3 , wherein forming said word line trench isolation region comprises recessing said conductive material, forming a spacer in said recess and performing an etch process so as to remove a portion of said conductive material by using said spacer as an etch mask.

5. A method, comprising:
forming buried sense lines so as to be in contact with a buried doped semiconductor region, said sense lines comprising an isolation region extending through a stack of doped semiconductor layers comprising a doped top layer of a first conductivity type and a doped bottom layer of a second conductivity type, wherein an entirety of each of said buried sense lines is positioned at a depth below said stack of doped semiconductor layers;
forming trench isolation regions in said stack of doped semiconductor layers, each of said trench isolation regions being formed laterally between respective two of adjacent sense lines, wherein forming said trench isolation regions comprises:
forming spacers adjacent said isolation region for each of said sense lines:
etching said stack of doped semiconductor materials using said isolation region and said spacers as an etch mask to form trenches; and
filling said trenches with an insulating material to define said trench isolation regions;

forming buried word lines in said stack of doped semiconductor layers and in said trench isolation regions, each of said buried word lines having a first side laterally adjacent to a first pillar structure and having a second side laterally opposite to said first side, said second side being formed laterally adjacent to a second pillar structure; and
forming a first bit line contact region and a second bit line contact region, said first bit line contact region being connected to a first plurality of pillar structures, said second bit line contact region being connected to a second plurality of pillar structures, said first plurality of pillar structures being associated with a first one of said sense lines, said second plurality of pillar structures being associated with a second one of said sense lines, said first and second pluralities of pillar structures being associated with the same word line.

6. The method of claim 5 , wherein forming said trench isolation regions comprises performing a self-aligned patterning process with respect to said sense line isolation regions so as to form trenches in said stack of semiconductor layers.

7. The method of claim 5 , further comprising forming a conductive buried sense line substantially parallel to said word lines, wherein said conductive buried sense line is positioned laterally adjacent to the bottom layer of each of said first plurality of pillar structures so as to define the final pillar shape to form a back capacitor for enhanced memory capacitance.

8. The method of claim 7 , wherein said buried sense line contacts said buried doped semiconductor region along the entire length of said buried doped semiconductor region.

9. The method of claim 7 , wherein said first buried sense line contacts said buried doped semiconductor region along an entire length of said buried doped semiconductor region associated with said first plurality of pillar structures.

10. The method of claim 9 , wherein said second buried sense line contacts said buried doped semiconductor region along an entire length of said buried doped semiconductor region associated with said second plurality of pillar structures.

Assignees

• Baars Peter
• Schloesser Till
• Globalfoundries Inc

Inventors

• Baars Peter
• Schloesser Till

Classifications

• H10D30/711 Primary

  having floating bodies · CPC title

• H01L29/7841 Primary

  Electricity · mapped topic

• H01L27/10802

  Electricity · mapped topic

• H10B12/20

  DRAM devices comprising floating-body transistors, e.g. floating-body cells · CPC title