Semiconductor devices and methods of manufacturing
US-12166025-B2 · Dec 10, 2024 · US
3D semiconductor device and structure with back-bias
US9136153B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9136153-B2 |
| Application number | US-201213492395-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jun 8, 2012 |
| Priority date | Nov 18, 2010 |
| Publication date | Sep 15, 2015 |
| Grant date | Sep 15, 2015 |
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Abstract
Official abstract text for this publication.
A 3D semiconductor device, including: a first layer including first transistors; a first interconnection layer interconnecting the first transistors and includes aluminum or copper; a second layer including second transistors; where the second transistors are aligned to the first transistors with a less than 40 nm alignment error, and where the second layer is overlying the first interconnection layer, and where at least one of the second transistors has a back-bias structure designed to modify the performance of at least one of the second transistors.
First claim
Opening claim text (preview).
What is claimed is: 1. A 3D semiconductor device, comprising: a first layer comprising first transistors; a first interconnection layer interconnecting said first transistors and comprises aluminum or copper; a second layer comprising second transistors; and at least one through-layer via; wherein said at least one through-layer via comprises a conductive path through said second layer, wherein said at least one through-layer via has a diameter less than 200 nm, wherein…
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Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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Frequently asked questions
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- What does patent US9136153B2 cover?
- A 3D semiconductor device, including: a first layer including first transistors; a first interconnection layer interconnecting the first transistors and includes aluminum or copper; a second layer including second transistors; where the second transistors are aligned to the first transistors with a less than 40 nm alignment error, and where the second layer is overlying the first interconnectio…
- Who is the assignee on this patent?
- Or-Bach Zvi, Sekar Deepak C, Cronquist Brian, and 4 more
- What technology area does this patent fall under?
- Primary CPC classification H10P72/74. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Sep 15 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).