Firmware interface with durable memory storage
US-2015370302-A1 · Dec 24, 2015 · US
Semiconductor memory having both volatile and non-volatile functionality and method of operating
US9153333B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9153333-B2 |
| Application number | US-201414307424-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jun 17, 2014 |
| Priority date | Oct 24, 2007 |
| Publication date | Oct 6, 2015 |
| Grant date | Oct 6, 2015 |
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Abstract
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Semiconductor memory having both volatile and non-volatile modes and methods of operation. A semiconductor storage device includes a plurality of memory cells each having a floating body for storing, reading and writing data as volatile memory. The device includes a floating gate or trapping layer for storing data as non-volatile memory, the device operating as volatile memory when power is applied to the device, and the device storing data from the volatile memory as non-volatile memory when power to the device is interrupted.
First claim
Opening claim text (preview).
That which is claimed is: 1. A method of operating a semiconductor storage device comprising a plurality of memory cells connected in series and each having a floating body for storing, reading and writing data as volatile memory, and a floating gate or trapping layer above said floating body for storing data as non-volatile memory, the method comprising: transferring the data stored in the floating bodies, by a parallel, non-algorithmic process, to the floating gates or trapping…
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- G11C14/0018Primary
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
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- What does patent US9153333B2 cover?
- Semiconductor memory having both volatile and non-volatile modes and methods of operation. A semiconductor storage device includes a plurality of memory cells each having a floating body for storing, reading and writing data as volatile memory. The device includes a floating gate or trapping layer for storing data as non-volatile memory, the device operating as volatile memory when power is app…
- Who is the assignee on this patent?
- Zeno Semiconductor Inc
- What technology area does this patent fall under?
- Primary CPC classification G11C14/0018. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Oct 06 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).