Vertical floating body storage transistors formed in bulk devices and having buried sense and word lines
US-9484457-B2 · Nov 1, 2016 · US
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Baars Peter patents
Baars Peter holds 6 patents in our database, with recent filings and technology areas summarized below.
| Metric | Value |
|---|---|
| Total patents | 6 |
| Recent patents | 0 |
| First publication | Jan 6, 2015 |
| Latest publication | Nov 1, 2016 |
Filing trend
Year-over-year patent counts for this assignee.
Recent patents
Latest publications where this party is an assignee.
Method of forming conductive contacts on a semiconductor device with embedded memory and the resulting device
US-9034753-B2 · May 19, 2015 · US
Method of forming contacts for devices with multiple stress liners
US-9023696-B2 · May 5, 2015 · US
Method of forming spacers that provide enhanced protection for gate electrode structures
US-8987104-B2 · Mar 24, 2015 · US
SRAM integrated circuits and methods for their fabrication
US-8946821-B2 · Feb 3, 2015 · US
Notable patents
Representative or frequently cited publications from precomputed assignee stats.
Vertical floating body storage transistors formed in bulk devices and having buried sense and word lines
US-9484457-B2 · Nov 1, 2016 · US
Method of forming conductive contacts on a semiconductor device with embedded memory and the resulting device
US-9034753-B2 · May 19, 2015 · US
Method of forming contacts for devices with multiple stress liners
US-9023696-B2 · May 5, 2015 · US
Method of forming spacers that provide enhanced protection for gate electrode structures
US-8987104-B2 · Mar 24, 2015 · US
SRAM integrated circuits and methods for their fabrication
US-8946821-B2 · Feb 3, 2015 · US
Top CPC classifications
Most common classification codes in this portfolio.
| CPC | Patents |
|---|---|
| H10D30/792 | 2 |
| H10D64/021 | 1 |
| H10D30/6748 | 1 |
| H10D30/6713 | 1 |
| H10D30/601 | 1 |
Technology areas
Mapped technology topics for this assignee.
| Technology | Patents |
|---|---|
| Electricity | 6 |