Multi-layer circuit member with reference circuit

US9462676B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9462676-B2
Application numberUS-201013508401-A
CountryUS
Kind codeB2
Filing dateNov 4, 2010
Priority dateNov 6, 2009
Publication dateOct 4, 2016
Grant dateOct 4, 2016

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A multi-layer circuit member includes first and second electrically connected reference regions. At least a portion of a signal conductor is in proximity to the first region and a circuit component is in proximity to the second region. An area of increased impedance exists between the first and second electrically connected regions.

First claim

Opening claim text (preview).

The invention claimed is: 1. A multi-layer circuit member comprising: first and second spaced apart, generally parallel conductive reference planes; an electrically conductive via extending between the first and second reference planes to electrically interconnect the first and second reference planes; a first signal conductor adjacent a first region of the first reference plane; at least one component adjacent to and operative to transfer energy to the second reference plane; and an elongated area of increased impedance in the first reference plane located between the first region of the first reference plane and the via, wherein the elongated area of increased impedance is an elongated slot in the first reference plane, the elongated slot having two opposing sides and two ends, wherein the two sides of the elongated slot are not in direct electrical communication except at the ends of the elongated slot or through the via. 2. The multi-layer circuit member of claim 1 , wherein the first signal conductor is one of a plurality of first signal conductors lying in a common plane generally parallel to the first reference plane and at least a portion of the plurality of first signal conductors are adjacent the first region of the first reference plane. 3. The multi-layer circuit member of claim 2 , wherein the plurality of first signal conductors are configured to be electrically coupled to the first reference plane. 4. The multi-layer circuit member of claim 2 , wherein the plurality of first signal conductors include at least two pairs of preferentially coupled first signal conductors. 5. The multi-layer circuit member of claim 1 , further including a plurality of first signal conductors adjacent the first reference plane and positioned on a side of the first reference plane opposite the second reference plane, and a plurality of second signal conductors adjacent the second reference plane and positioned on a side of the second reference plane opposite the first reference plane. 6. The multi-layer circuit member of claim 1 , wherein the at least one component is a second signal conductor electrically coupled to the second reference plane. 7. The multi-layer circuit member of claim 1 , wherein the first signal conductor has a first length and the elongated slot has a length greater than approximately half of the first length of the first signal conductor. 8. The multi-layer circuit member of claim 1 , wherein the first signal conductor has a first length and the elongated slot has a length at least as long as approximately the first length of the first signal conductor. 9. A multi-layer circuit member comprising: first and second spaced apart, generally parallel conductive reference planes; an electrically conductive via extending between the first and second reference planes to electrically interconnect the first and second reference planes; a first signal conductor adjacent a first region of the first reference plane; at least one component adjacent to and operative to transfer energy to the second reference plane; and an elongated area of increased impedance in the first reference plane located between the first region of the first reference plane and the via, wherein the area of increased impedance is a region with a cross-hatched conductive pattern. 10. A multi-layer circuit member comprising: first and second spaced apart, generally parallel conductive reference planes; an electrically conductive via extending between the first and second reference planes to electrically interconnect the first and second reference planes; a first signal conductor adjacent a first region of the first reference plane; at least one component adjacent to and operative to transfer energy to the second reference plane; and an elongated area of increased impedance in the first reference plane located between the first region of the first reference plane and the via, wherein the area of increased impedance is a region with a roughened surface. 11. A multi-layer circuit member comprising: a conductive reference plane including first and second electrically connected regions; at least a portion of a first signal conductor adjacent the first region of the reference plane; at least one second signal conductor including a portion extending through an opening in the reference plane adjacent the second region of the reference plane; and an area of increased impedance between the first and second electrically connected regions of the reference plane, wherein the area of increased impedance is an elongated slot in the reference plane, the elongated slot having two opposing sides and two ends, wherein the two sides of the elongated slot are not in direct electrical communication except at the ends of the elongated slot or through the via. 12. The multi-layer circuit member of claim 11 , further including a second conductive reference plane, the conductive reference plane and the second conductive plane being spaced apart and generally parallel, the at least one second signal conductor including a second portion adjacent the second reference plane. 13. The multi-layer circuit member of claim 11 , wherein the first signal conductor is one of a plurality of first signal conductors lying in a common plane generally parallel to the reference plane and at least a portion of the plurality of first signal conductors are adjacent and electrically coupled to the first region of the reference plane. 14. A filtering module comprising: a housing formed of a dielectric material; a magnetics assembly mounted on the housing including at least one filtering transformer, each filtering transformer being interconnected to a plurality of conductors; and a multi-layer circuit member mounted on the housing, the circuit member including first and second spaced apart, generally parallel reference planes, a junction at the first reference plane to electrically interconnect the first and second reference planes, a first signal conductor electrically connected to one of the plurality of conductors of the magnetics assembly, the first signal conductor being adjacent to the first reference plane, a first portion of the first signal conductor being adjacent to a first region of the first reference plane, at least one component operative to transfer energy to the second reference plane, and an elongated slot in the first reference plane located between the first region of the first reference plane and the junction. 15. The filtering module of claim 14 , wherein the at least one component is a second signal conductor electrically connected to one of the plurality of conductors of the magnetics assembly and electrically coupled to the second reference plane. 16. The filtering module of claim 14 , wherein the filtering transformer includes a plurality of wires wrapped therearound.

Assignees

Inventors

Classifications

  • Shields or metal cases · CPC title

  • Providing micro- or nanometer scale roughness on a metal surface, e.g. by plating of nodules or dendrites · CPC title

  • Plated through-holes specially for multilayer circuits, e.g. having connections to inner circuit layers · CPC title

  • Lay-out of balanced signal pairs, e.g. differential lines or twisted lines · CPC title

  • Non-printed filter · CPC title

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What does patent US9462676B2 cover?
A multi-layer circuit member includes first and second electrically connected reference regions. At least a portion of a signal conductor is in proximity to the first region and a circuit component is in proximity to the second region. An area of increased impedance exists between the first and second electrically connected regions.
Who is the assignee on this patent?
Regnier Kent E, Molex Llc
What technology area does this patent fall under?
Primary CPC classification H05K1/0227. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Oct 04 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).