Multi-layer circuit member and assembly therefor

Patent metadata

Field	Value
Publication number	US-9345128-B2
Application number	US-201013508209-A
Country	US
Kind code	B2
Filing date	Nov 4, 2010
Priority date	Nov 6, 2009
Publication date	May 17, 2016
Grant date	May 17, 2016

Abstract

A multi-layer circuit member includes a conductive reference plane with first and second electrically connected regions. A pair of signal conductors are in proximity to the first region and a circuit component is in proximity to the second region. An area of increased impedance exists between the first and second electrically connected regions.

First claim

The invention claimed is:

1. A multi-layer circuit member comprising:
a reference plane formed of a conductive material, the reference plane including first and second regions that are electrically connected;
a first pair of signal conductors adjacent the first region of the reference plane;
a second pair of signal conductors adjacent the second region of the reference plane, wherein the first and second pair of signal conductors are adjacent each other; and
an elongated area of increased impedance in the reference plane located between the first and second electrically connected regions, the elongated area of increased impedance positioned between the first and second pair of signal conductors.

2. The multi-layer circuit member of claim 1 , wherein the elongated area of increased impedance is a slot in the reference plane.

3. The multi-layer circuit member of claim 2 , further including a second conductive reference plane, the first and second pairs of signal conductors being positioned between the reference plane and the second reference plane.

4. The multi-layer circuit member of claim 3 , wherein the second reference plane includes third and fourth regions that are electrically connected and that are separated by a second slot in the second reference plane, the third and fourth regions being generally aligned with the first and second regions of the reference plane and the second slot being generally aligned with the slot.

5. The multi-layer circuit member of claim 4 , further including a plurality of first and second conductive members electrically connecting the reference plane and the second reference plane, the plurality of first conductive members being positioned on opposite sides of the first pair of signal conductors and the plurality of second conductive members being positioned on opposite sides of the second pair of signal conductors.

6. The multi-layer circuit member of claim 5 , wherein the plurality of first conductive members are positioned generally parallel to the first pair of signal conductors on one side of the slot and the second slot and the plurality of second conductive members are positioned generally parallel to the second pair of signal conductors on an opposite side of the slot and the second slot.

7. The multi-layer circuit member of claim 2 , wherein the slot extends generally to an edge of the reference plane.

8. The multi-layer circuit member of claim 1 , wherein the reference plane further includes a third region adjacent and electrically connected to the first region and a fourth region adjacent and electrically connected to the second region, and further including a third pair of signal conductors adjacent the third region of the reference plane and a fourth pair of signal conductors adjacent the fourth region of the reference plane.

9. The multi-layer circuit member of claim 8 , further including second and third elongated areas of increased impedance in the reference plane, the second area of increased impedance being located between the first and third electrically connected regions and the third area of increased impedance being located between the second and fourth electrically connected regions.

10. The multi-layer circuit member of claim 8 , wherein the first and third pairs of signal conductors are electrically connected to channels of the circuit member that transmit signals and the second and fourth pairs of signal conductors are electrically connected to channels of the circuit member that receive signals.

11. The multi-layer circuit member of claim 1 , wherein the reference plane is a generally planar member positioned between insulative layers and the electrical connection between the first and second regions is within the plane of the reference plane.

12. The multi-layer circuit member of claim 4 , wherein the reference plane and the second reference plane each further include a respective third region adjacent and electrically connected to its first region and a respective fourth region adjacent and electrically connected to its second region, and further including a third pair of signal conductors adjacent and between the third regions and a fourth pair of signal conductors adjacent and between the fourth regions.

13. The multi-layer circuit member of claim 12 , wherein the reference plane and the second reference plane each include second and third slots, the second slots being located between the first and third electrically connected regions and the third slots being located between the second and fourth electrically connected regions.

14. The multi-layer circuit member of claim 1 , wherein conductors of the first and second pairs of signal conductors each have a length and the area of increased impedance has a length equal to at least approximately 75% of the length of the signal conductors.

Assignees

• Regnier Kent E
• Molex Llc

Inventors

• Regnier Kent E

Classifications

• H05K1/0227 Primary

  Split or nearly split shielding or ground planes · CPC title

• H01R13/6625

  with capacitive component · CPC title

• H01R13/6633

  with inductive component, e.g. transformer · CPC title

• H05K1/0248

  Skew reduction or using delay lines · CPC title

• H05K2201/10189

  Non-printed connector · CPC title