Method and apparatus for testing a semiconductor device

Patent metadata

Field	Value
Publication number	US-9459316-B2
Application number	US-201113225816-A
Country	US
Kind code	B2
Filing date	Sep 6, 2011
Priority date	Sep 6, 2011
Publication date	Oct 4, 2016
Grant date	Oct 4, 2016

Abstract

The present disclosure provides a method for testing a semiconductor device. The method includes providing a test unit and an electronic circuit that is electrically coupled to the test unit. The method includes performing a multi-dimensional sweeping process. The multi-dimensional sweeping process includes sweeping a plurality of different electrical parameters across their respective ranges. The method includes monitoring a performance of the electronic circuit during the multi-dimensional sweeping process. The monitoring includes identifying optimum values of the different electrical parameters that yield a satisfactory performance of the electronic circuit. The method includes testing the test unit using the optimum values of the different electrical parameters.

First claim

What is claimed is:

1. A method, comprising:
providing a test unit and an electronic circuit that is electrically coupled to the test unit;
performing a multi-dimensional sweeping process, wherein the multi-dimensional sweeping process includes sweeping a plurality of different electrical parameters across their respective ranges;
monitoring a performance of the electronic circuit during the multi-dimensional sweeping process, wherein the monitoring includes identifying optimum values of the different electrical parameters that yield a satisfactory performance of the electronic circuit; and
testing the test unit using the optimum values of the different electrical parameters.

2. The method of claim 1 , wherein:
the electrical parameters include a terminal test voltage and a power supply voltage; and
the performance of the electronic circuit includes a leakage current.

3. The method of claim 2 , wherein the performing the multi-dimensional sweeping process includes:
performing a coarse sweep of both the terminal test voltage and the power supply voltage to identify the optimum value of the power supply voltage; and
thereafter performing a fine sweep of the terminal test voltage to identify the optimum value of the terminal test voltage.

4. The method of claim 3 , wherein:
the coarse sweep is carried out using a nested loop, a sweep of the terminal test voltage being the inner loop, and a sweep of the power supply voltage being the outer loop; and
the coarse sweep has greater sweep steps than the fine sweep.

5. The method of claim 1 , wherein the providing is carried out in a manner such that the electronic circuit includes a plurality of electronic switching devices and a plurality of control logic devices.

6. The method of claim 5 , wherein the multi-dimensional sweeping process is performed while at least a subset of the electronic switching devices is deactivated.

7. The method of claim 1 , further including: concurrently duplicating at least a portion of the performing the multi-dimensional sweeping process, the monitoring, and the testing for one or more additional test units.

8. The method of claim 1 , wherein the test units include at least one of: a resistor and a transistor.

9. The method of claim 1 , further including: providing a plurality of testing pads and a plurality of additional test units;
wherein:
each testing pad is coupled to the test unit and the additional test units through the electronic circuit; and
at least one of: the performing, the monitoring, and the testing is performed through at least a subset of the testing pads.

10. The method of claim 1 ,
wherein the electrical parameters include a first test voltage and a second test voltage to be applied concurrently to the electronic circuit; and
wherein the monitoring of the performance of the electronic circuit includes:
measuring noise over a first range of the first test voltage and a first range of the second test voltage to determine a first minimum noise value;
based on the first minimum noise value, determining a second range of the first test voltage and a second range of the second test voltage; and
measuring the noise over the second range of the first test voltage and the second range of the second test voltage to determine a second minimum noise value that is less than or equal to the first minimum noise value.

11. The method of claim 10 , wherein the noise accounts for a leakage current associated with the electronic circuit.

12. The method of claim 10 , wherein the measuring of the noise over the first range of the first test voltage and the first range of the second test voltage is performed at a larger granularity than the measuring of the noise over the second range of the first test voltage and the second range of the second test voltage.

13. The method of claim 10 , wherein the first test voltage is a power supply voltage and the second test voltage is a terminal test voltage.

14. The method of claim 10 , wherein the second range of the first test voltage is a single value.

15. The method of claim 1 , wherein the performing of the multi-dimensional sweeping process and the monitoring of the performance of the electronic circuit are performed using a first set of test pads of the electronic circuit, and wherein the testing of the electronic circuit is performed using a second set of test pads of the electronic circuit that is different from the first set of test pads.

16. The method of claim 15 , wherein the first set of test pads and the second set of test pads have at least one pad in common.

17. The method of claim 1 , wherein the performing of the multi-dimensional sweeping process and the monitoring of the performance of the electronic circuit are performed using a first set of test pads of the electronic circuit, the method further comprising:
repeating the performing of the multi-dimensional sweeping process and the monitoring of the performance of the electronic circuit using a second set of test pads of the electronic circuit that is different from the first set of test pads.

18. The method of claim 17 , wherein the first set of test pads and the second set of test pads have at least one pad in common.

Assignees

• Huang Szu-Chia
• Shao Jhih Jie
• Chung Tang-Hsuan
• Tseng Huan Chi
• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Huang Szu-Chia
• Shao Jhih Jie
• Chung Tang-Hsuan
• Tseng Huan Chi

Classifications

• G01R31/30 Primary

  Marginal testing, e.g. by varying supply voltage (testing computers during standby operation or idle time G06F11/22) · CPC title

• G01R31/3004

  Current or voltage test · CPC title