Semiconductor integrated circuit device having function for detecting degradation of semiconductor device and method of driving the same

Patent metadata

Field	Value
Publication number	US-9429618-B2
Application number	US-201514723833-A
Country	US
Kind code	B2
Filing date	May 28, 2015
Priority date	Jan 30, 2015
Publication date	Aug 30, 2016
Grant date	Aug 30, 2016

Abstract

A semiconductor integrated circuit device having a function for detecting degradation of a semiconductor device and a method of driving the same are disclosed. The semiconductor integrated circuit device includes an NMOS transistor electrically coupled to a PMOS transistor and configured to constitute an inverter together with the PMOS transistor, a first stress application unit electrically coupled to the PMOS transistor and configured to apply stress to the PMOS transistor, and a second stress application unit electrically coupled to the NMOS transistor and configured to apply the stress to the NMOS transistor.

First claim

What is claimed is:

1. A semiconductor integrated circuit device comprising:
an NMOS transistor electrically coupled to a PMOS transistor and configured to constitute an inverter together with the PMOS transistor;
a first stress application unit electrically coupled to the PMOS transistor and configured to apply stress to the PMOS transistor;
a second stress application unit electrically coupled to the NMOS transistor and configured to apply the stress to the NMOS transistor,
a first output terminal unit withdrawn from a connection node of the PMOS transistor and the NMOS transistor;
a second output terminal unit electrically coupled to a source of the PMOS transistor; and
a loop forming unit configured to electrically couple the second output terminal unit and a source of the NMOS transistor,
wherein the first and second output terminals and the loop forming unit are configured to measure a current value of a first current path flowing through the PMOS transistor and a current value of a second current path flowing through the NMOS transistor.

2. The semiconductor integrated circuit device of claim 1 , further comprising:
a plurality of switches configured to allow the first current path flowing through the PMOS transistor and the second current path flowing through the NMOS transistor to be individually formed.

3. The semiconductor integrated circuit device of claim 1 , wherein the first stress application unit is configured to allow a gate-drain voltage of the PMOS transistor to have a negative value.

4. The semiconductor integrated circuit device of claim 3 , wherein the first stress application unit includes:
a transfer gate electrically coupled to a drain of the PMOS transistor and driven in response to first and second control signals; and
a sub NMOS transistor electrically coupled to the transfer gate and configured to discharge a signal transmitted from the transfer gate to a ground terminal in response to an input signal of the inverter.

5. The semiconductor integrated circuit device of claim 1 , wherein the second stress application unit is configured to allow a gate-drain voltage of the NMOS transistor to have a positive value.

6. The semiconductor integrated circuit device of claim 5 , wherein the second stress application unit includes:
a sub PMOS transistor electrically coupled to a driving voltage terminal and driven in response to an input signal of the inverter; and
a transfer gate electrically coupled between the sub PMOS transistor and a drain of the NMOS transistor and driven in response to first and second control signals.

7. The semiconductor integrated circuit device of claim 1 , wherein an input signal of the inverter is an AC input signal.

8. The semiconductor integrated circuit device of claim 1 , wherein an input signal of the inverter is a DC input signal.

9. The semiconductor integrated circuit device of claim 1 , further comprising:
an AC input signal generating unit configured to provide an input signal of the inverter;
a DC input signal generating unit configured to provide the input signal of the inverter; and
a selection unit configured to select one of the AC input signal generating unit and the DC input signal generating unit.

10. A semiconductor integrated circuit device comprising:
an inverter including a PMOS transistor and an NMOS transistor;
an input unit configured to transfer an input signal to gates of the PMOS transistor and the NMOS transistor;
a first stress application unit electrically coupled between the gate and a drain of the PMOS transistor and configured to apply stress to the PMOS transistor;
a second stress application unit electrically coupled between the gate and a drain of the NMOS transistor and configured to apply the stress to the NMOS transistor;
a first output terminal unit withdrawn from an output node of the inverter;
a second output terminal unit withdrawn from a source node of the PMOS transistor;
a loop forming unit configured to electrically couple a source node of the NMOS transistor and the second output terminal unit;
a first switching unit electrically coupled between the drain of the PMOS transistor and an output node of the inverter;
a second switching unit electrically coupled between the output node of the inverter and the drain of the NMOS transistor;
a third switching unit located in the second output terminal unit; and
a fourth switching unit located in the loop forming unit.

11. The semiconductor integrated circuit device of claim 10 , wherein when a current path flowing through the PMOS transistor is formed, the first and third switching units are turned on, and the second and fourth switching units are turned off.

12. The semiconductor integrated circuit device of claim 10 , wherein when a current path flowing through the NMOS transistor is formed, the first and third switching units are turned off, and the second and fourth switching units are turned on.

13. The semiconductor integrated circuit device of claim 11 , wherein the input unit includes:
an AC input signal generating unit;
a DC input signal generating unit; and
a selection unit configured to select one of the AC input signal generating unit and the DC input signal generating unit.

14. The semiconductor integrated circuit device of claim 10 , wherein the first stress application unit includes:
a transfer gate electrically coupled to the drain of the PMOS transistor and driven in response to first and second control signals; and
a sub NMOS transistor electrically coupled to the transfer gate and configured to discharge a signal transmitted from the transfer gate to a ground terminal in response to an input signal of the inverter.

15. The semiconductor integrated circuit device of claim 10 , wherein the second stress application unit includes:
a sub PMOS transistor electrically coupled to a driving voltage terminal and driven in response to an input of the inverter; and
a transfer gate electrically coupled between the sub PMOS transistor and the drain of the NMOS transistor and driven in response to first and second control signals.

16. A method of measuring a degree of degradation in each of a PMOS transistor and an NMOS transistor in an inverter structure including the PMOS transistor, the NMOS transistor, a first switching unit electrically coupled between the drain of the PMOS transistor and an output node of the inverter, a second switching unit electrically coupled between the output node of the inverter and the drain of the NMOS transistor, a third switching unit located in the second output terminal unit; and a fourth switching unit located in the loop forming unit, the method comprising:
measuring an initial first current path flowing through the PMOS transistor in a state in which a current path flowing through the NMOS transistor is blocked;
applying stress to the PMOS transistor by providing a gate-drain voltage of the PMOS transistor having a negative level;
checking whether a first current path flowing through the PMOS transistor in which the stress is received is generated when the first and third switching units are turned on and the second and fourth switching units are turned off; and
measuring the degree of degradation in the PMOS transistor through a variation in the first current path.

17. The method of claim 16 , further comprising:
measuring an initial second current path flowing through the NMOS transistor in a state in which a current path flowing through the PMOS transistor is blocked;
applying the stress to the NMOS transistor by providing a gate-drain v

Assignees

• Sk Hynix Inc

Inventors

• Hwang Jeong Tae

Classifications

• H03K17/6872

  using complementary field-effect transistors · CPC title

• H03K19/0005 Primary

  Modifications of input or output impedance · CPC title

• G01R31/2874

  related to temperature · CPC title

• H03K17/102

  in field-effect transistor switches · CPC title

• H03K19/018521

  of complementary type, e.g. CMOS · CPC title