Dual-rail encoding

Patent metadata

Field	Value
Publication number	US-9455706-B2
Application number	US-201414313776-A
Country	US
Kind code	B2
Filing date	Jun 24, 2014
Priority date	Jun 24, 2014
Publication date	Sep 27, 2016
Grant date	Sep 27, 2016

Abstract

Embodiments may include a method, system and apparatus for providing for encoded dual-rail signal communications in asynchronous circuitry. A dual rail signal pair is received. The dual rail signal pair comprises a first value indicative of a first wait state, a second value indicative of a logic value of a first bit, a third value indicative of a second wait state and a first logic value of a second bit, and/or a fourth value indicative of second wait state and a second logic value of said second bit.

First claim

What is claimed:

1. A method comprising:
receiving, at an encoder, a first signal representing a first bit;
receiving, at the encoder, a second signal representing a second bit;
encoding, at the encoder, said first and second bits into a first dual-rail signal that spans first, second, and third time periods, wherein said dual-rail signal comprises: a two-bit representation of a first wait state during said first time period; a two-bit representation of said first bit during said second time period; and a two-bit representation of both a second wait state and said second bit during said third time period; and
providing said first dual-rail signal from the encoder to a dual-rail receiver via a first wire pair.

2. The method of claim 1 , further comprising:
determining, at a decoder receiving the first-rail signal, that said second wait state has occurred based upon the two-bit representation of said first wait state during said first time period.

3. The method of claim 2 , wherein determining that said second wait state has occurred comprises at least one of:
determining that said second wait state has occurred in response to determining said value is 00 in response to said second bit being 0; or
determining that said second wait state has occurred in response to determining said value is 11 in response to said second bit being 1.

4. The method of claim 1 , wherein:
receiving said first signal and said second signal comprises receiving said first and second signals from a dual-rail transmitter over a first distance; and
providing said first dual-rail signal comprises transmitting said first dual-rail signal over a second distance, wherein said second distance is greater than said first distance.

5. The method of claim 1 , further comprising:
receiving, at said encoder via a second wire pair, a third signal representing a third bit;
receiving, at said encoder via a third wire pair, a fourth signal representing a fourth bit;
encoding, at said encoder, said third and fourth bits into a second dual-rail signal that spans first, second, and third time periods, wherein said second dual-rail signal comprises a two-bit representation of a third wait state during said first time period, a two-bit representation of said third bit during said second time period, and, and a two-bit representation of both said fourth bit and a fourth wait state during said third time period; and
providing said second dual-rail signal from said encoder to said dual-rail receiver via a second wire pair.

6. The method of claim 5 , further comprising said dual-rail receiver asserting an acknowledgement signal during said second time period and de-asserting said acknowledgement signal during said third time period in response to receiving at least one of:
said two-bit representation of said first bit during said second time period, said two-bit representation of said second wait state and said second bit during said third time period; or
said two-bit representation of said third bit during said second time period, said two-bit representation of said second wait state during said third time period and said two-bit representation of said fourth bit during said third time period.

7. An apparatus comprising:
a dual-rail converter comprising:
an input to receive a first signal representing a first bit, and a second input to receive a second signal representing a second bit;
an encoder operatively coupled to said first and second inputs, said encoder configured to encode said first and second signals into a dual-rail signal that spans first, second, and third time periods, wherein said dual-rail signal comprises a two-bit representation of a first wait state during said first time period, a two-bit representation of said first bit during said second time period, and a two-bit representation of both second wait state and said second bit during said third time period; and

an output coupled to a first wire pair to transmit said dual-rail signal.

8. The apparatus of claim 7 , wherein the two-bit representation of the second wait state is 00 in response to said second bit being 0 and wherein the two-bit representation of the second wait state is 11 in response to said second bit being 1.

9. The apparatus of claim 7 , further comprising:
a dual-rail transmitter operatively coupled to said first and second inputs, wherein said dual-rail transmitter is configured to concurrently transmit a plurality of dual-rail signals indicative of a plurality of bits; and
a dual-rail receiver operatively coupled to said first wire pair, wherein said dual-rail receiver is configured to receive at least one encoded dual-rail signals.

10. The apparatus of claim 9 , wherein said encoder is positioned at a first distance from said dual-rail transmitter, and at a second distance from said dual-rail receiver, wherein said second distance is greater than said first distance.

11. The apparatus of claim 7 , further comprising:
a processor for executing an instruction, the processor coupled to said dual-rail converter.

12. The dual-rail encoder of claim 7 , wherein:
the first input is coupled to a second wire pair to receive the first signal; and
the second input is coupled to a third wire pair to receive the second signal.

13. The method of claim 1 , wherein:
receiving the first signal comprises receiving the first signal at the encoder via a second wire pair; and
receiving the second signal comprises receiving the second signal at the encoder via a third wire pair.

Assignees

• Advanced Micro Devices Inc

Inventors

• Sadowski Greg

Classifications

• H03K19/21

  EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical · CPC title

• H03K19/0002 Primary

  Multistate logic (H03K19/02 takes precedence) · CPC title