Receiving an I/O signal in multiple voltage domains

Patent metadata

Field	Value
Publication number	US-9473141-B2
Application number	US-201414512626-A
Country	US
Kind code	B2
Filing date	Oct 13, 2014
Priority date	Oct 13, 2014
Publication date	Oct 18, 2016
Grant date	Oct 18, 2016

Abstract

Embodiments disclosed herein include an I/O module with multiple level shifters that establish a plurality of voltage domains. Using the level shifters, the I/O module converts data signals in a core logic voltage domain to data signals in an external voltage domain. In one embodiment, when transmitting data signals to an external device, the I/O module level shifts the data signals from a core logic voltage domain to a low voltage domain. The I/O module then level shifts the data signals from the low voltage domain to an intermediate voltage domain. The I/O module may further shift the data signals from the intermediate voltage domain to both a low voltage domain and a high voltage domain. Using the data signals from both of these domains, the I/O module outputs the data signals in a voltage domain corresponding to a communication technique used to transmit data to the external device.

First claim

What is claimed is:

1. An I/O module, comprising:
an n-type transistor;
a p-type transistor, wherein a drain of the p-type transistor is coupled to a drain of the n-type transistor;
an I/O pad electrically coupled to the drains of the p-type and n-type transistors, the I/O pad is configured to receive a first data signal in a first voltage domain;
a voltage feedback control circuit configured to:
apply a gate signal to both gates of the p-type and n-type transistors, and
control the gate signal such that a voltage of the gate signal follows a voltage of the first data signal unless the voltage of the first data signal exceeds an upper limit voltage and unless the voltage of the first data signal falls below a lower limit voltage, the upper and lower limit voltages defining an intermediate voltage domain;

a receiver circuit configured to output a second data signal responsive to receiving the gate signal from the voltage feedback circuit; and
a level shifter configured to covert the second data signal into a second voltage domain, wherein the converted data signal carries the same data as the first data signal.

2. The I/O module of claim 1 , wherein the voltage feedback control circuit is configured to:
maintain the voltage of the gate signal at the upper limit voltage when the voltage of the first data signal exceeds the upper limit voltage; and
maintain the voltage of the gate signal at the lower limit voltage when the voltage of first data signal falls below the lower limit voltage.

3. The I/O module of claim 1 , wherein the level shifter is configured to transmit the converted data signal core logic of an integrated circuit, wherein the second voltage domain is a core logic voltage domain and is different from the first voltage domain.

4. The I/O module of claim 1 , wherein the receiver circuit is a Schmitt trigger.

5. The I/O module of claim 1 , further comprising a direct electrical connection between the I/O pad and the voltage feedback control circuit.

6. The I/O module of claim 1 , further comprising:
at least two additional n-type transistors connected in series to the n-type transistor; and
at least two additional p-type transistors connected in series to the p-type transistor.

7. The I/O module of claim 1 , wherein the intermediate voltage domain includes a smaller range of voltages than the first voltage domain and the second voltage domain includes a smaller range of voltages than the intermediate voltage domain.

8. An integrated circuit, comprising:
core logic; and
an I/O module communicatively coupled to the core logic, the I/O module comprising:
an n-type transistor;
a p-type transistor, wherein a drain of the p-type transistor is coupled to a drain of the n-type transistor;
an I/O pad electrically coupled to the drains of the p-type and n-type transistors, the I/O pad is configured to receive a first data signal in a first voltage domain;
a voltage feedback control circuit configured to:
generate a gate signal to control both gates of the p-type and n-type transistors, and
control the gate signal such that a voltage of the gate signal follows a voltage of the first data signal unless the voltage of the first data signal exceeds an upper limit voltage and unless the voltage of the first data signal falls below a lower limit voltages, the upper and lower limit voltage defining an intermediate voltage domain;

a receiver circuit configured to output a second data signal responsive to receiving the gate signal from the voltage feedback circuit; and
a level shifter configured to covert the second data signal into a second voltage domain, wherein the converted data signal carries the same data as the first data signal.

9. The integrated circuit of claim 8 , wherein the voltage feedback control circuit is configured to:
maintain the voltage of the gate signal at the upper limit voltage when the voltage of the first data signal exceeds the upper limit voltage; and
maintain the voltage of the gate signal at the lower limit voltage when the voltage of first data signal falls below the lower limit voltage.

10. The integrated circuit of claim 8 , wherein the receiver circuit is a Schmitt trigger.

11. The integrated circuit of claim 8 , wherein the I/O module further comprises a direct electrical connection between the I/O pad and the voltage feedback control circuit.

12. The integrated circuit of claim 8 , wherein the I/O module further comprises further comprises:
at least two additional n-type transistors connected in series to the n-type transistor; and
at least two additional p-type transistors connected in series to the p-type transistor.

13. The integrated circuit of claim 8 , wherein the intermediate voltage domain includes a smaller range of voltages than the first voltage domain and the second voltage domain includes a smaller range of voltages than the intermediate voltage domain.

Assignees

• Globalfoundries Inc

Inventors

• Kerr Michael K
• Lawson William F

Classifications

• H03K19/017509 Primary

  Interface arrangements · CPC title

• H03K19/0002

  Multistate logic (H03K19/02 takes precedence) · CPC title

• H03K19/0013

  in field effect transistor circuits · CPC title