Non-volatile boolean logic operation circuit and operation method thereof

Patent metadata

Field	Value
Publication number	US-9473137-B2
Application number	US-201514867030-A
Country	US
Kind code	B2
Filing date	Sep 28, 2015
Priority date	Jun 20, 2014
Publication date	Oct 18, 2016
Grant date	Oct 18, 2016

Abstract

A non-volatile Boolean logic operation circuit, including: two input ends; an output end; a first resistive switching element M 1 , the first resistive switching element M including a positive electrode and a negative electrode; and a second resistive switching element M 2 , the second resistive switching element M 2 including a positive electrode and a negative electrode. The negative electrode of the first resistive switching element M 1 operates as a first input end of the logic operation circuit. The negative electrode of the second resistive switching element M 2 operates as a second input end of the logic operation circuit. The positive electrode of the second resistive switching element M 2 is connected to the positive electrode of the first resistive switching element M 1 , and a connected end thereof operates as the output end of the logic operation circuit.

First claim

The invention claimed is:

1. A non-volatile Boolean logic operation circuit, comprising:
a) a first resistive switching element, the first resistive switching element comprising a positive electrode and a negative electrode; and
b) a second resistive switching element, the second resistive switching element comprising a positive electrode and a negative electrode;

wherein:
said negative electrode of said first resistive switching element operates as a first input end of said logic operation circuit and is adapted to receive a first input signal;
said negative electrode of said second resistive switching element operates as a second input end of said logic operation circuit and is adapted to receive a second input signal; and
said positive electrode of said second resistive switching element is connected to said positive electrode of said first resistive switching element, and a connected end thereof operates as an output end of said logic operation circuit and is adapted to output a logic operation result of the first input signal and the second input signal.

2. The circuit of claim 1 , wherein
in operation, forward writing of an initial state W=1 is facilitated by applying high level to said first input end, and low level to said second input end, and reverse writing of said initial state W =1 is facilitated by applying low level to said first input end, and high level to said second input end;
resistive switching of said first resistive switching element and said second resistive switching element is facilitated by inputting a signal A to said first input end, and a signal B to said second input end according to an initial state of each of said resistive switching elements, and results of said input signals A and B after logic operation are stored according to said resistive switching;
outputting of a storage state of said first resistive switching element is facilitated by inputting a read voltage to said first input end and suspending said second input end, and outputting of a storage state of said second resistive switching element is facilitated by inputting said read voltage to said second input end and suspending said first input end; and
said input signal A or said input signal B is a high-level signal or a low-level signal, and an amplitude of said read voltage is less than that of a voltage of each of said resistive switching elements as resistive switching occurs, namely a threshold voltage thereof.

3. The circuit of claim 1 , wherein an operation result of said non-volatile Boolean logic operation circuit is expressed by: L=A· B · W · R +(Ā+B)· W ·R+Ā·B·W·R+(A+ B )·W· R ; where A represents a signal input to said first input end, B represents a signal input to said second input end, W represents a write direction of initialization, and R represents a readout direction of said operation result.

4. The circuit of claim 1 , wherein said first resistive switching element and said second resistive switching element are memristors.

5. An operation method of the non-volatile Boolean logic operation circuit of claim 1 , the method comprising:
1) controlling an initial state of each of said first resistive switching element and said second resistive switching element by inputting a high-level signal or a low-level signal to said first input end, and inputting a signal having an opposite level thereto to said second input end;

wherein:
an initial state of said first resistive switching element being written as a high resistance state as a signal input to said first input end is high level and a signal input to said second input end is low level, and an initial state of said second resistive switching element being written as a low resistance state, and this type of writing being labeled as forward writing W=1;
said initial state of said first resistive switching element being written as a low resistance state as said signal input to said first input end is low level and said signal input to said second input end is high level, and said initial state of said second resistive switching element being written as a high resistance state, and

this type of writing being labeled as reverse writing W =1; and
said high resistance state of each of said resistive switching elements operating to store a logic 0, and said low resistance state of said resistive switching element operating to store a logic 1;
2) changing storage states of said first resistive switching element and said second resistive switching element by inputting a signal A to said first input end, and a signal B to said second input end;

wherein:
said storage state of said first resistive switching element being changed from said initial state to said low resistance state, and said storage state of said second resistive switching element being changed from said initial state to said high resistance state as said signal A is low level and said signal B is high level;
said storage state of said first resistive switching element being changed from said initial state to said high resistance state, and said storage state of said second resistive switching element being changed from said initial state to said low resistance state as said signal A is high level and said signal B is low level; and
said first resistive switching element and said second resistive switching element being maintained in said initial state as both said signal A and said signal B are high level or low level;
3) conducting read operation of an output end by inputting a read voltage to said first input end or said second input end;

wherein:
said storage state of said first resistive switching element being obtained by reading a current of said first resistive switching element at said output end as said read voltage is input to said first input end and said second input end is suspended, and this type of reading being labeled as R=1;
said storage state of said second resistive switching element being obtained by reading a current of said second resistive switching element at said output end as said first input end is suspended and said read voltage is input to said second input end, and this type of reading being labeled as R =1; and
an amplitude of said read voltage being less than that of a voltage of each of said resistive switching elements as resistive switching occurs, namely a threshold voltage thereof; and
4) obtaining an operation result of said non-volatile Boolean logic operation circuit according to A, B, R and W: L=A· B · W · R +(Ā+B)· W ·R+Ā·B·W·R+(A+ B )·W· R ; where A represents a signal input to said first input end, B represents a signal input to said second input end, W represents a write direction of initialization, and R represents a readout direction of said operation result.

6. The method of claim 5 , wherein sixteen types of Boolean logic operation are facilitated based on said operation result of said non-volatile Boolean logic operation circuit, and comprise:
1) facilitating logic 0 operation by applying high level and low level so that W=0, A=0, B=0, and R=0;
2) facilitating logic 1 operation by applying high level and low level so that W=0, A=1, B=0, and R=0;
3) facilitating logic operation of P by applying high level and low level so that W=0, A=P, B=0, and R=0, in which P is an input signal and has a value of 0 or 1;
4) facilitating logic operation of Q by applying high level and low level so that W=1, A=0, B=Q, and R=1, in which Q is an input signal and has a value of 0 or 1;
5) facilitating logic operation of P by applying high level and low level so that W=1, A=P, B=1, and R=1;
6) facilitating logic operation of Q by applying high level and low level so that A=1, B=Q, W=0, and R=0;
7) facilitating logic operation of P+ Q by applying high level and low level so tha

Assignees

• Univ Huazhong Science Tech

Inventors

• Miao Xiangshui
• Zhou Yaxiong
• Li Yi
• Sun Huajun

Classifications

• H03K19/0002 Primary

  Multistate logic (H03K19/02 takes precedence) · CPC title

• H03K19/0813

  Threshold logic · CPC title

• H03K19/20

  characterised by logic function, e.g. AND, OR, NOR, NOT circuits (H03K19/003 - H03K19/01 take precedence) · CPC title

• H03K19/0021

  Modifications of threshold (for electronic switching or gating H03K17/30) · CPC title