Bidirectional data exchange circuit

Patent metadata

Field	Value
Publication number	US-9356597-B2
Application number	US-201314108405-A
Country	US
Kind code	B2
Filing date	Dec 17, 2013
Priority date	Dec 17, 2012
Publication date	May 31, 2016
Grant date	May 31, 2016

Abstract

A bidirectional data exchange circuit ( 10 ) includes a buffer ( 16 ) having paired terminals (A1 . . . A8, B1 . . . B8), a transfer direction input ( 20 ), an input ( 42 ) for controlling the transfer direction, and a logic gate ( 50 ). In the logic gate ( 50 ), the output is connected to the transfer direction input ( 20 ), an input is connected to the input ( 42 ) for controlling the transfer direction, this input being further connected to a first reference potential (V cc ) through a resistor ( 52 ), and the other input is connected to a terminal (A1) of the buffer ( 16 ) and to the first reference potential (V cc ) through a resistor ( 54; 154 ), and the terminal (B1) of the buffer ( 16 ), matched with the terminal (A1) of the buffer to which is connected the other input of the logic gate ( 50 ) being connected to a second reference potential through a resistor ( 56 ). The order of the first and second reference potentials and the nature of the logic gate ( 50 ) are such that, after a first transfer direction control of the buffer in one direction, the matched terminals (A1) force the logic gate ( 50 ) into a predetermined state independent of the value of the signal on the direction control input ( 42 ).

First claim

The invention claimed is:

1. A bidirectional data exchange circuit ( 10 ) comprising:
a buffer ( 16 ) including:
a first set of terminals (A1 . . . A8) and a second set of terminals (B1 . . . B8) the terminals of which are matched pairwise for a bidirectional data exchange between two matched terminals of both sets;
a transfer direction input ( 20 ) between two matched terminals from an input to an output, the input being placed at a high impedance state in the absence of voltage on these terminals;

an input ( 42 ; 142 ) for controlling the transfer direction; and
a logic gate ( 50 ; 150 ) for which:
the output is connected to the transfer direction input ( 20 ) of the buffer ( 16 );
an input is connected to the input for controlling the transfer direction ( 42 ; 142 ), this input being further connected to a first reference potential (V cc ; 0) through a resistor ( 52 ; 152 ); and
the other input is connected to a terminal (A1; B1) of the buffer ( 16 ) and to the first reference potential (V cc ; 0) through a resistor ( 54 ; 154 );

the terminal (B1; A1) of the buffer ( 16 ) matched with the terminal (A1; B1) of the buffer to which is connected the other input of the logic gate ( 50 ; 150 ) being connected to a second reference potential (0; V cc ) through a resistor ( 56 ; 156 );
and in that the order of the first and second reference potentials and the nature of the logic gate ( 50 ; 150 ) are such that, after a first transfer direction control of the buffer in one direction, the matched terminals (A1; B1) force the logic gate ( 50 ; 150 ) into a predetermined state independent of the value of the signal on the direction control input ( 42 ; 142 ).

2. The exchange circuit ( 10 ) according to claim 1 , wherein the logic gates is an AND gate ( 50 ), and the second reference potential is lower than the first reference potential.

3. The exchange circuit ( 10 ) according to claim 1 , wherein the logic gate is an OR gate ( 150 ) and the second reference potential is higher than the first reference potential.

4. The logic circuit according to claim 1 , wherein the buffer ( 16 ) includes an input ( 22 ) for an activation signal, preventing any transfer between two matched terminals in the absence of an activation signal.

5. The logic circuit according to claim 1 , wherein the buffer ( 16 ) includes two matched auxiliary terminals (A2, B2) different from the matched terminals (A1, B1) in connection with the direction control input ( 20 ), for which:
the auxiliary terminal (A2; B2) of the same set as the terminal (A1; B1) connected to the logic gate ( 50 ; 150 ) is connected:
to an output ( 44 ; 144 ) for providing a piece of information representative of the transfer direction on the one hand and,
through a resistor ( 58 ; 160 ), to one of the first and second reference potentials (V cc ; 0) on the other hand, and

the other auxiliary terminal (B2; A2) is connected through a resistor ( 60 ; 162 ) to the other one of the first and second reference potentials (V cc ; 0).

Assignees

• Thales Sa

Inventors

• Pubert Laurent
• Pichet Jerome
• Grimonprez Benjamin
• Collange Thierry

Classifications

• H03K19/0002 Primary

  Multistate logic (H03K19/02 takes precedence) · CPC title

• G06F13/4072

  Drivers or receivers (G06F13/4086 takes precedence; for multistate logic circuits H03K19/0002) · CPC title