Receiving an i/o signal in multiple voltage domains

Patent metadata

Field	Value
Publication number	US-2016105181-A1
Application number	US-201414569097-A
Country	US
Kind code	A1
Filing date	Dec 12, 2014
Priority date	Oct 13, 2014
Publication date	Apr 14, 2016
Grant date	—

Abstract

Embodiments disclosed herein include an I/O module with multiple level shifters that establish a plurality of voltage domains. Using the level shifters, the I/O module converts data signals in a core logic voltage domain to data signals in an external voltage domain. In one embodiment, when transmitting data signals to an external device, the I/O module level shifts the data signals from a core logic voltage domain to a low voltage domain. The I/O module then level shifts the data signals from the low voltage domain to an intermediate voltage domain. The I/O module may further shift the data signals from the intermediate voltage domain to both a low voltage domain and a high voltage domain. Using the data signals from both of these domains, the I/O module outputs the data signals in a voltage domain corresponding to a communication technique used to transmit data to the external device.

First claim

What is claimed is:

1 . A method comprising:
receiving a first data signal in a first voltage domain at a input/output (I/O) pad, wherein the I/O pad is electrically connected to a node that is between a p-type transistor and an n-type transistor; applying a gate signal to both gates of the p-type and n-type transistors; controlling the gate signal such that a voltage of the gate signal follows a voltage of the first data signal unless the voltage of the first data signal exceeds an upper limit voltage and unless the voltage of the first data signal falls below a lower limit voltage, the upper and lower limit voltages defining an intermediate voltage domain; outputting a second data signal responsive to receiving the gate signal at a receiver circuit; and converting the second data signal outputted from the receiver circuit into a second voltage domain, wherein the converted data signal carries the same data as the first data signal.

2 . The method of claim 1 , wherein controlling the gate signal further comprises:
maintaining the voltage of the gate signal at the upper limit voltage when the voltage of the first data signal exceeds the upper limit voltage; and maintaining the voltage of the gate signal at the lower limit voltage when the voltage of the first data signal falls below the lower limit voltage.

3 . The method of claim 1 , further comprising:
transmitting the converted data signal to core logic of an integrated circuit, wherein the second voltage domain is a core logic voltage domain and is different from the first voltage domain.

4 . The method of claim 1 , wherein the receiver circuit is a Schmitt trigger.

5 . The method of claim 1 , wherein converting the second data signal into the second voltage domain is performed using a level shifter.

6 . The method of claim 1 , wherein the n-type transistor is connected in series to two additional n-type transistors and the p-type transistor is connected in series to two additional p-type transistors.

7 . The method of claim 1 , wherein the intermediate voltage domain includes a smaller range of voltages than the first voltage domain and the second voltage domain includes a smaller range of voltages than the intermediate voltage domain.

Assignees

• IBM

Inventors

• Kerr Michael K
• Lawson William F

Classifications

• H03K19/0013

  in field effect transistor circuits · CPC title

• H03K19/0002

  Multistate logic (H03K19/02 takes precedence) · CPC title

• H03K19/017509 Primary

  Interface arrangements · CPC title