Semiconductor device and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-9422151-B1
Application number	US-201514858414-A
Country	US
Kind code	B1
Filing date	Sep 18, 2015
Priority date	Sep 18, 2015
Publication date	Aug 23, 2016
Grant date	Aug 23, 2016

Abstract

A semiconductor device includes a substrate and a movable membrane proximal to the substrate. The semiconductor device further includes a mesa over the substrate and protruded from a surface of the substrate toward the movable membrane. The mesa includes a strike hitting portion configured to receive a striking force from the membrane and a hybrid stress buffer under the strike hitting portion, wherein the hybrid stress buffer includes at least two layers which are distinguishable by a difference in hardness.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a cavity;
a membrane in the cavity;
a substrate on one side of the cavity; and
a mesa protruded from a surface of the substrate and toward the membrane, wherein the mesa comprises:
a material proximal to the membrane;
a first buffer layer between the substrate and the material, and at least partially covered by the material; and
a second buffer layer between the substrate and the first buffer layer, and partially covered by the first buffer layer, wherein the material contacts the second buffer layer, and the second buffer layer includes a hardness greater than a hardness of the first buffer layer.

2. The semiconductor device of claim 1 , wherein the membrane is movable in the cavity and the material is configured to be in contact with the membrane while the membrane is relocated toward the surface.

3. The semiconductor device of claim 1 , wherein a hardness of the material is greater than a hardness of the first buffer layer.

4. The semiconductor device of claim 1 , wherein the first buffer layer is partially between the second buffer layer and the material.

5. The semiconductor device of claim 1 , wherein the first buffer layer is symmetrical with respect to the material.

6. The semiconductor device of claim 1 , wherein a sidewall of the first buffer layer is surrounded by the material.

7. The semiconductor device of claim 1 , wherein a top surface of the first buffer layer is surrounded by the material.

8. The semiconductor device of claim 1 , wherein the first buffer layer comprises a paired portions and a gap between the paired portions is filled with the material.

9. The semiconductor device of claim 1 , wherein the first buffer layer is enclosed by the material.

10. A semiconductor device, comprising:
a substrate;
a movable membrane proximal to the substrate; and
a mesa over the substrate and protruded from a surface of the substrate toward the movable membrane, wherein the mesa comprises:
a strike hitting portion configured to receive a striking force from the membrane; and
a hybrid stress buffer under the strike hitting portion, wherein the hybrid stress buffer includes at least two layers which are distinguishable by a difference in hardness.

11. The semiconductor device of claim 10 , wherein the at least two layers is respectively in contact with the strike hitting portion.

12. The semiconductor device of claim 10 , wherein one of the at least two layers is in a cross shape.

13. The semiconductor device of claim 10 , wherein one of the at least two layers is in a quadrilateral or circular shape.

14. The semiconductor device of claim 10 , wherein a lateral geometric center of the strike hitting portion is aligned with a lateral geometric center of one of the at least two layers.

15. The semiconductor device of claim 10 , wherein a center line of the strike hitting portion is aligned with a center line of the one of the at least two layers.

16. The semiconductor device of claim 10 , wherein at least one of the at least two layers comprises a hardness smaller than a hardness of the strike hitting portion.

17. A semiconductor device, comprising:
a substrate;
a movable membrane proximal to the substrate; and
a mesa protruded from a surface of the substrate and toward the membrane, wherein the mesa comprises:
a first layer configured to receive a striking force from the membrane;
a second layer over the substrate; and
a third layer between the first layer and the second layer, the first layer partially contacting the second layer and partially contacting the third layer, and the third layer including a hardness smaller than a hardness of the first layer and a hardness of the second layer.

18. The semiconductor device of claim 17 , wherein the third layer is partially covered at a top surface thereof by a strike hitting potion of the first layer.

19. The semiconductor device of claim 17 , wherein at least a sidewall of the third layer is exposed from the first layer.

20. The semiconductor device of claim 17 , wherein the third layer comprises at least two disjoined parts symmetrically disposed with respect to the first layer.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Tai Wen-Chuan
• Kalnitsky Alexander
• Huang Hsin-Ting
• Chen Hsiang-Fu
• Lee Jiou-Kang
• Shen Ching-Kai

Classifications

• B81C1/00158

  Diaphragms, membranes (manufacture process for semi-permeable inorganic membranes B01D67/0039) · CPC title

• B81B2203/0127

  Diaphragms, i.e. structures separating two media that can control the passage from one medium to another; Membranes, i.e. diaphragms with filtering function · CPC title

• B81B3/0097 Primary

  Devices comprising flexible or deformable elements not provided for in groups B81B3/0002 - B81B3/0094 · CPC title

• B81B3/0072

  For controlling internal stress or strain in moving or flexible elements, e.g. stress compensating layers · CPC title

• B81B3/0013 Primary

  Structures dimensioned for mechanical prevention of stiction, e.g. spring with increased stiffness · CPC title