Semiconductor structure and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-2017297902-A1
Application number	US-201615130077-A
Country	US
Kind code	A1
Filing date	Apr 15, 2016
Priority date	Apr 15, 2016
Publication date	Oct 19, 2017
Grant date	—

Abstract

A semiconductor structure includes a first substrate including a cavity extended into the first substrate, a device disposed within the cavity, a first dielectric layer disposed over the first substrate and a first conductive structure surrounded by the first dielectric layer, and a second substrate including a second dielectric layer disposed over the second substrate and a second conductive structure surrounded by the second dielectric layer, wherein the first conductive structure is bonded with the second conductive structure and the first dielectric layer is bonded with the second dielectric layer to seal the cavity.

First claim

1 . A semiconductor structure, comprising:
a first substrate including a cavity extended into the first substrate, a device disposed within the cavity, a first dielectric layer disposed over the first substrate and a first conductive structure surrounded by the first dielectric layer; and a second substrate including a second dielectric layer disposed over the second substrate and a second conductive structure surrounded by the second dielectric layer, wherein the first conductive structure is interfaced with the second conductive structure and the first dielectric layer is interfaced with the second dielectric layer to seal the cavity.

2 . The semiconductor structure of claim 1 , wherein the first conductive structure is aligned with the second conductive structure, or the first substrate is aligned with the second substrate.

3 . The semiconductor structure of claim 1 , wherein the first conductive structure is complementary to the second conductive structure.

4 . The semiconductor structure of claim 1 , wherein a top surface of the first conductive structure is at a same level as a top surface of the first dielectric layer, or a top surface of the second conductive structure is a same level as a top surface of the second dielectric layer.

5 . The semiconductor structure of claim 1 , wherein the cavity is enclosed by the first substrate, the first dielectric layer and the second dielectric layer.

6 . The semiconductor structure of claim 1 , wherein the first conductive structure is extended along a periphery of the first substrate, or the second conductive structure is extended along a periphery of the second substrate.

7 . The semiconductor structure of claim 1 , wherein the first conductive structure or the second conductive structure is in a partially closed loop or in a ring shape.

8 . The semiconductor structure of claim 1 , wherein the first conductive structure or the second conductive structure is electrically connected with a circuitry disposed over the second substrate.

9 . The semiconductor structure of claim 1 , wherein the first conductive structure and the second conductive structure include copper, and the first dielectric layer and the second dielectric layer include oxide or nitride.

10 . The semiconductor structure of claim 1 , wherein the device is an accelerometer or includes a proof mass.

11 . The semiconductor structure of claim 1 , wherein the cavity is in vacuum.

12 . A semiconductor structure, comprising:
a first substrate; a second substrate disposed opposite to the first substrate; a dielectric layer disposed between the first substrate and the second substrate; a conductive structure disposed within the dielectric layer; a chamber extended from the first substrate to the dielectric layer and enclosed by the first substrate and the dielectric layer; and a device disposed within the chamber,
wherein an interface is disposed within the dielectric layer and the conductive structure, and is extended from a sidewall of the dielectric layer towards the chamber and at least partially across the dielectric layer and the conductive structure.

13 . The semiconductor structure of claim 12 , wherein the interface is substantially orthogonal to the sidewall of the dielectric layer.

14 . The semiconductor structure of claim 12 , wherein the interface divides the dielectric layer into an upper portion and a lower portion, or the interface divides the conductive structure into an upper portion and a lower portion.

15 . The semiconductor structure of claim 12 , wherein the interface at least partially surrounds the chamber.

16 . The semiconductor structure of claim 12 , wherein the chamber is hermetic.

17 - 20 . (canceled)

21 . A semiconductor structure, comprising:
a first substrate including a cavity extended into the first substrate, a MEMS device disposed within the cavity, a first dielectric layer disposed over the first substrate, and a first conductive structure at least partially exposed from the first dielectric layer; and a second substrate including a second dielectric layer disposed over the second substrate and a second conductive structure at least partially exposed from the second dielectric layer,
wherein the first conductive structure exposed from the first dielectric layer is interfaced with the second conductive structure exposed from the second dielectric layer, and the first dielectric layer is interfaced with the second dielectric layer.

22 . The semiconductor structure of claim 21 , wherein a first interface between the first conductive structure and the second conductive structure is at substantially same level as a second interface between the first dielectric layer and the second dielectric layer.

23 . The semiconductor structure of claim 21 , wherein the first conductive structure is contacted with the second conductive structure.

24 . The semiconductor structure of claim 21 , wherein the cavity is enclosed by the first conductive structure or the second conductive structure.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Lin Hung-Hua
• Liu Ping-Yin
• Liu Kuan-Liang
• Tsai Chia-Shiung
• Kalnitsky Alexander

Classifications

• B81B2207/012

  the micromechanical device and the control or processing electronics being separate parts in the same package · CPC title

• B81C2203/0118

  Bonding a wafer on the substrate, i.e. where the cap consists of another wafer · CPC title

• B81B7/0032 Primary

  Packages or encapsulation (processes for packaging MEMS B81C1/00261; packaging of smart-MEMS B81C1/0023) · CPC title

• B81C1/00261

  Processes for packaging MEMS devices (MEMS packages B81B7/0032, packaging of smart-MEMS B81C1/0023) · CPC title

• B81C1/00269 Primary

  Bonding of solid lids or wafers to the substrate · CPC title