Integrated circuit and method of forming an integrated circuit

Patent metadata

Field	Value
Publication number	US-9418937-B2
Application number	US-201113315642-A
Country	US
Kind code	B2
Filing date	Dec 9, 2011
Priority date	Dec 9, 2011
Publication date	Aug 16, 2016
Grant date	Aug 16, 2016

Abstract

An integrated circuit includes a base element and a copper element over the base element, the copper element having a thickness of at least 5 μm and a ratio of average grain size to thickness of less than 0.7.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a semiconductor substrate, components of a power device being disposed in the semiconductor substrate; and
a copper element over the semiconductor substrate and electrically connected to one of the components of the power device, the copper element having a thickness of at least 5 μm and a ratio of average grain size to thickness of less than 0.7, wherein a modal value of the grain size distribution of the copper element is more than 2 μm and less than 5 μm, wherein the average grain size of the copper element is less than 4.0 μm.

2. The semiconductor device according to claim 1 , wherein the ratio of average grain size to thickness is less than 0.55.

3. The semiconductor device according to claim 1 , wherein the thickness of the copper element is more than 5 μm.

4. The semiconductor device according to claim 1 , wherein the average grain size is approximately independent from the thickness of the copper element.

5. The semiconductor device integrated circuit according to claim 1 , wherein the copper element is a layer, a patterned layer or a wiring.

6. The semiconductor device according to claim 1 , wherein the average grain size of the copper element is less than 3.5 μm.

7. The semiconductor device according to claim 1 , wherein the modal value of the grain size distribution of the copper element is less than 4 μm.

8. The semiconductor device according to claim 1 , wherein the copper element comprises copper and at least one additive selected from the group consisting of chloride (Cl), sulfur (S) and at least one organic additive.

9. The semiconductor device according to claim 8 , wherein the copper element comprises chloride and sulfur as admixtures.

10. The semiconductor device according to claim 9 , wherein the copper element comprises further admixtures, the amount of chloride being larger than any amount of the other admixtures.

11. The semiconductor device according to claim 1 , further comprising a hard layer comprising at least one of NiP, NiMoP, NiPd, Ni(X)P, and Ni(X,Y)P, the hard layer being disposed over the copper element, and wherein X and Y denote further elements.

12. The semiconductor device according to claim 1 , wherein the copper element comprises chloride as an admixture, wherein a ratio of a time-of-flight secondary ion mass spectroscopy signal of chloride with respect to a time-of-flight secondary ion mass spectroscopy signal of copper is larger than 1.25%.

13. The semiconductor device according to claim 1 , wherein the copper element comprises sulfur as an admixture, wherein a ratio of a time-of-flight secondary ion mass spectroscopy signal of sulfur with respect to a time-of-flight secondary ion mass spectroscopy signal of copper is larger than 0.075%.

14. The semiconductor device of claim 1 , further comprising a power transistor.

15. A method of manufacturing a semiconductor device comprising forming a copper element over a semiconductor substrate, components of a power device being disposed in the semiconductor substrate, so that the copper element has a thickness of at least 5 μm and a ratio of average grain size to thickness of less than 0.7, wherein a modal value of the grain size distribution of the copper element is more than 2 μm and less than 5 μm, wherein the average grain size of the copper element is less than 4.0 μm, and so that the copper element is electrically connected to one of the components of the power device.

16. The method of claim 15 , wherein forming the copper element comprises electroplating under conditions set so that the ratio of average grain size to thickness is less than 0.7.

17. An integrated circuit comprising a power transistor including:
a semiconductor substrate, components of the power transistor being disposed in the semiconductor substrate; and
a copper element over the semiconductor substrate, the copper element having a thickness of at least 5 μm and a ratio of average grain size to thickness of less than 0.7,
wherein a modal value of the grain size distribution of the copper element is more than 2 μm and less than 5 μm, wherein the average grain size of the copper element is less than 4.0 μm.

Assignees

• Detzel Thomas
• Gross Johann
• Illing Robert
• Krug Maximilian
• Lanzerstorfer Sven Gustav
• Nelhiebel Michael
• Robl Werner
• Rogalli Michael
• Woehlert Stefan
• Infineon Technologies Ag

Inventors

• Detzel Thomas
• Gross Johann
• Illing Robert
• Krug Maximilian
• Lanzerstorfer Sven Gustav
• Nelhiebel Michael
• Robl Werner
• Rogalli Michael
• Woehlert Stefan

Classifications

• H10P14/47

  Electrolytic deposition, i.e. electroplating; Electroless plating · CPC title

• H10W40/037

  Assembling together parts thereof · CPC title

• H10W20/425 Primary

  Barrier, adhesion or liner layers · CPC title

• H10W40/255 Primary

  having a laminate or multilayered structure, e.g. direct bond copper [DBC] ceramic substrates · CPC title

• H01L21/2885

  Electricity · mapped topic