Semiconductor device

US9412874B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9412874-B2
Application numberUS-201514706282-A
CountryUS
Kind codeB2
Filing dateMay 7, 2015
Priority dateMay 10, 2012
Publication dateAug 9, 2016
Grant dateAug 9, 2016

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  1. Title

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  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A highly reliable semiconductor device the yield of which can be prevented from decreasing due to electrostatic discharge damage is provided. A semiconductor device is provided which includes a gate electrode layer, a first gate insulating layer over the gate electrode layer, a second gate insulating layer being over the first gate insulating layer and having a smaller thickness than the first gate insulating layer, an oxide semiconductor layer over the second gate insulating layer, and a source electrode layer and a drain electrode layer electrically connected to the oxide semiconductor layer. The first gate insulating layer contains nitrogen and has a spin density of 1×10 17 spins/cm 3 or less corresponding to a signal that appears at a g-factor of 2.003 in electron spin resonance spectroscopy. The second gate insulating layer contains nitrogen and has a lower hydrogen concentration than the first gate insulating layer.

First claim

Opening claim text (preview).

The invention claimed is: 1. A semiconductor device comprising: a gate electrode layer; a first gate insulating layer containing silicon and nitrogen adjacent to the gate electrode layer; a second gate insulating layer containing silicon and nitrogen over the first gate insulating layer; a first oxide semiconductor layer containing more indium than gallium adjacent to the second gate insulating layer; and a second oxide semiconductor layer over the first oxide semiconductor layer. 2. The semiconductor device according to claim 1 , wherein a content of indium in the second oxide semiconductor layer is lower than or equal to a content of gallium. 3. The semiconductor device according to claim 1 , wherein the gate electrode layer contains copper. 4. The semiconductor device according to claim 1 , further comprising a source electrode layer and a drain electrode layer over the second oxide semiconductor layer. 5. The semiconductor device according to claim 1 , wherein the first gate insulating layer is provided over the gate electrode layer, and the first oxide semiconductor layer is provided over the second gate insulating layer. 6. The semiconductor device according to claim 1 , wherein the first gate insulating layer has a spin density of 1×10 17 spins/cm 3 or less corresponding to a signal that appears at a g-factor of 2.003 in electron spin resonance spectroscopy. 7. The semiconductor device according to claim 1 , wherein the second gate insulating layer has a lower hydrogen concentration than the first gate insulating layer. 8. The semiconductor device according to claim 1 , wherein the semiconductor device is one selected from the group consisting of a table having a display portion, a television device, a computer, and a tablet terminal. 9. A semiconductor device comprising: a gate electrode layer; a first gate insulating layer containing silicon and nitrogen adjacent to the gate electrode layer; a second gate insulating layer containing silicon and nitrogen over the first gate insulating layer; a first oxide semiconductor layer containing more indium than gallium adjacent to the second gate insulating layer; and a second oxide semiconductor layer over the first oxide semiconductor layer, wherein a thickness of the second gate insulating layer is smaller than a thickness of the first gate insulating layer. 10. The semiconductor device according to claim 9 , wherein a content of indium in the second oxide semiconductor layer is lower than or equal to a content of gallium. 11. The semiconductor device according to claim 9 , wherein the gate electrode layer contains copper. 12. The semiconductor device according to claim 9 , further comprising a source electrode layer and a drain electrode layer over the second oxide semiconductor layer. 13. The semiconductor device according to claim 9 , wherein the first gate insulating layer is provided over the gate electrode layer, and the first oxide semiconductor layer is provided over the second gate insulating layer. 14. The semiconductor device according to claim 9 , wherein the first gate insulating layer has a spin density of 1×10 17 spins/cm 3 or less corresponding to a signal that appears at a g-factor of 2.003 in electron spin resonance spectroscopy. 15. The semiconductor device according to claim 9 , wherein the second gate insulating layer has a lower hydrogen concentration than the first gate insulating layer. 16. The semiconductor device according to claim 9 , wherein the semiconductor device is one selected from the group consisting of a table having a display portion, a television device, a computer, and a tablet terminal.

Assignees

Inventors

Classifications

  • having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device · CPC title

  • Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate · CPC title

  • Subject matter not provided for in other groups of this subclass · CPC title

  • the insulator comprising nitrogen, e.g. nitrides, oxynitrides or nitrogen-doped materials · CPC title

  • being perpendicular to the channel plane · CPC title

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Frequently asked questions

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What does patent US9412874B2 cover?
A highly reliable semiconductor device the yield of which can be prevented from decreasing due to electrostatic discharge damage is provided. A semiconductor device is provided which includes a gate electrode layer, a first gate insulating layer over the gate electrode layer, a second gate insulating layer being over the first gate insulating layer and having a smaller thickness than the first …
Who is the assignee on this patent?
Semiconductor Energy Lab
What technology area does this patent fall under?
Primary CPC classification H10D30/6704. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Aug 09 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 12 related publications on this page (citations in our corpus or others sharing the same primary CPC).