Semiconductor device

US8946702B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-8946702-B2
Application numberUS-201313860792-A
CountryUS
Kind codeB2
Filing dateApr 11, 2013
Priority dateApr 13, 2012
Publication dateFeb 3, 2015
Grant dateFeb 3, 2015

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A transistor includes oxide semiconductor stacked layers between a first gate electrode layer and a second gate electrode layer through an insulating layer interposed between the first gate electrode layer and the oxide semiconductor stacked layers and an insulating layer interposed between the second gate electrode layer and the oxide semiconductor stacked layers. The thickness of a channel formation region is smaller than the other regions in the oxide semiconductor stacked layers. Further in this transistor, one of the gate electrode layers is provided as what is called a back gate for controlling the threshold voltage. Controlling the potential applied to the back gate enables control of the threshold voltage of the transistor, which makes it easy to maintain the normally-off characteristics of the transistor.

First claim

Opening claim text (preview).

The invention claimed is: 1. A semiconductor device comprising: a first gate electrode layer over an insulating surface; a first insulating layer over the first gate electrode layer; oxide semiconductor stacked layers comprising a first oxide semiconductor layer and a second oxide semiconductor layer and overlapping with the first gate electrode layer with the first insulating layer interposed between the first gate electrode layer and the oxide semiconductor stacked layers;…

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What does patent US8946702B2 cover?
A transistor includes oxide semiconductor stacked layers between a first gate electrode layer and a second gate electrode layer through an insulating layer interposed between the first gate electrode layer and the oxide semiconductor stacked layers and an insulating layer interposed between the second gate electrode layer and the oxide semiconductor stacked layers. The thickness of a channel fo…
Who is the assignee on this patent?
Semiconductor Energy Lab
What technology area does this patent fall under?
Primary CPC classification H10D30/6755. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Feb 03 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).