Signed multiplier circuit utilizing a uniform array of logic blocks

Patent metadata

Field	Value
Publication number	US-9411554-B1
Application number	US-41704609-A
Country	US
Kind code	B1
Filing date	Apr 2, 2009
Priority date	Apr 2, 2009
Publication date	Aug 9, 2016
Grant date	Aug 9, 2016

Abstract

A signed multiplier circuit includes a two-dimensional array of substantially similar logic blocks. Each of the logic blocks is programmable to implement any of four multiply functions of first and second inputs, in which: the first and second inputs are both signed; the first and second inputs are both unsigned; the first input is signed and the second input is unsigned; and the first input is unsigned and the second input is signed. Each logic block includes rows and columns of sub-circuits, e.g., logical AND gates and full adders. One row and one column of each logic block include a programmably invertible AND gate, with the row and column being independently controlled. The ability to program the logic block to perform all four of these functions enables the combination of rows and columns of the logic blocks to build large signed multipliers of virtually any size.

First claim

What is claimed is:

1. A signed multiplier circuit, comprising:
a two-dimensional array of instances of a logic block, adjacent instances of the logic block being coupled one to another;
a plurality of pairs of configuration memory cells, each pair of configuration memory cells coupled to one of the instances of the logic block, respectively, wherein:
each instance of the logic block is programmable to implement a first multiply function of first and second inputs, wherein the first and second inputs are both signed;
each instance of the logic block is programmable to implement a second multiply function of the first and second inputs, wherein the first and second inputs are both unsigned;
each instance of the logic block is programmable to implement a third multiply function of the first and second inputs, wherein the first input is signed and the second input is unsigned;
each instance of the logic block is programmable to implement a fourth multiply function of the first and second inputs, wherein the first input is unsigned and the second input is signed; and
each instance of the logic block is responsive to the respective pair of configuration memory cells, and in each pair a first configuration memory cell indicates whether the first input to the instance of the logic block is signed or unsigned, and a second configuration memory cell indicates whether the second input to the instance of the logic block is signed or unsigned.

2. The signed multiplier circuit of claim 1 , wherein:
each instance of the logic block comprises M rows and N columns of sub-circuits, M and N being integers greater than one;
the sub-circuits in one column of the N columns each comprise a first plurality of logical AND gates having programmably inverted outputs; and
the sub-circuits in one row of the M rows each comprise a second plurality of logical AND gates having programmably inverted outputs.

3. The signed multiplier circuit of claim 2 , wherein:
each of the sub-circuits in the N−1 of the columns not including the one column comprises a logical AND gate and a full adder circuit, the full adder circuit having an input coupled to an output of the logical AND gate.

4. The signed multiplier circuit of claim 3 , wherein:
each of the sub-circuits in the one column comprises a logical AND gate, with no full adder circuit being included in the sub-circuit.

5. The signed multiplier circuit of claim 3 , wherein:
the logical AND gate in a single sub-circuit included in both the one column and the one row is inverted when one of the first and second inputs is signed and the other of the first and second inputs is unsigned, and is not inverted when both of the first and second inputs are signed or both of the first and second inputs are unsigned;
the logical AND gate in all sub-circuits in the one column except for the single sub-circuit is inverted when the first input is signed; and
the logical AND gate in all sub-circuits in the one row except for the single sub-circuit is inverted when the second input is signed.

6. The signed multiplier circuit of claim 2 , further comprising:
a first memory cell coupled to each sub-circuit in the one column, the first memory cell being coupled to programmably invert the output of the logical AND gate in each sub-circuit in the one column; and
a second memory cell coupled to each sub-circuit in the one row, the second memory cell being coupled to programmably invert the output of the logical AND gate in each sub-circuit in the one row.

7. The signed multiplier circuit of claim 2 , wherein M and N are both equal to eight.

8. The signed multiplier circuit of claim 1 , further comprising:
means for adding a value of “1” to an output of the two-dimensional array.

9. The signed multiplier circuit of claim 1 , wherein:
the two-dimensional array includes one column of instances of the logic block and one row of instances of the logic block intersecting at a single instance of the logic block that is included in both the one column and the one row;
the instances of the logic block in the one column are programmed to implement the third multiply function, with the exception of the single instance;
the instances of the logic block in the one row are programmed to implement the fourth multiply function, with the exception of the single instance;
the single instance is programmed to implement the first multiply function; and
at least one other instance of the logic block in the two-dimensional array is programmed to implement the second multiply function.

10. A signed multiplier circuit, comprising:
a two-dimensional array of instances of a logic block, adjacent instances of the logic block being coupled one to another, and each of the instances of the logic block being programmable to implement a first multiply function of first and second inputs, wherein each of the instances of the logic block includes:
M rows and N columns of sub-circuits, M and N being integers greater than one;
a first memory cell coupled to each of the sub-circuits in one column of the N columns, the first memory cell indicating whether the first input to the instance of the logic block is signed or unsigned; and
a second memory cell coupled to each of the sub-circuits in one row of the M rows, the second memory cell indicating whether the second input to the instance of the logic block is signed or unsigned.

11. The signed multiplier circuit of claim 10 , further comprising:
an exclusive OR gate having a first input coupled to the first memory cell, a second input coupled to the second memory cell, and an output coupled to a sub-circuit included in both the one column and the one row.

12. The signed multiplier circuit of claim 10 , wherein each of the sub-circuits in the one column comprises:
a first logical AND gate having an output;
a first inverter having an input coupled to the output of the logical AND gate and further having an output; and
a first programmable multiplexer having a first input coupled to the output of the first logical AND gate, a second input coupled to the output of the first inverter, and a select input coupled to the first memory cell.

13. The signed multiplier circuit of claim 12 , wherein each of the sub-circuits in the one row comprises:
a second logical AND gate having an output;
a second inverter having an input coupled to the output of the logical AND gate and further having an output; and
a second programmable multiplexer having a first input coupled to the output of the second logical AND gate, a second input coupled to the output of the second inverter, and a select input coupled to the second memory cell.

14. The signed multiplier circuit of claim 13 , further comprising:
an exclusive OR gate coupled between the first memory cell and the select input of a sub-circuit included in both the one row and the one column, and further coupled between the second memory cell and the select input of the sub-circuit included in both the one row and the one column.

15. The signed multiplier circuit of claim 10 , wherein:
each of the sub-circuits in the N−1 of the columns not including the one column comprises a logical AND gate and a full adder circuit, the full adder circuit having an input coupled to an output of the logical AND gate.

16. The signed multiplier circuit of claim 15 , wherein:
each of the sub-circuits in the one column comprises a programmably invertible logical AND gate coupled to the first memory cell, with no full adder circuit being included in the sub-circuit.

17. The signed multiplier circuit of claim

Assignees

• Young Steven P
• Gaide Brian C
• Xilinx Inc

Inventors

• Young Steven P
• Gaide Brian C

Classifications

• G06F7/5324 Primary

  partitioned, i.e. using repetitively a smaller parallel parallel multiplier or using an array of such smaller multipliers · CPC title

• G06F7/53

  in parallel-parallel fashion, i.e. both operands being entered in parallel (G06F7/533 takes precedence) · CPC title