Apparatuses, methods, and systems for memory interface circuit arbitration in a configurable spatial accelerator
US-2020410323-A1 · Dec 31, 2020 · US
in parallel-parallel fashion, i.e. both operands being entered in parallel (G06F7/533 takes precedence)
in parallel-parallel fashion, i.e. both operands being entered in parallel (G06F7/533 takes precedence) · Cooperative Patent Classification (CPC)
Computing, optics, measurement, and control technologies.
Related technology areas
Mapped technology topics for this CPC code.
| Metric | Value |
|---|---|
| CPC code | G06F7/53 |
| Official title | in parallel-parallel fashion, i.e. both operands being entered in parallel (G06F7/533 takes precedence) |
| Display label | in parallel-parallel fashion, i.e. both operands being entered in parallel (G06F7/533 takes precedence) |
| Total patents | 213 |
Filing trend
Year-over-year patent counts classified under this CPC code.
Filing activity over the last five years is stable.
| Year | Patents |
|---|---|
| 2015 | 7 |
| 2016 | 7 |
| 2017 | 8 |
| 2018 | 4 |
| 2019 | 11 |
| 2020 | 25 |
| 2021 | 19 |
| 2022 | 41 |
| 2023 | 38 |
| 2024 | 28 |
| 2025 | 17 |
| 2026 | 8 |
Representative patents
Representative publications under this CPC code from precomputed stats, or recent filings when stats are unavailable.
Neural network accelerator
US-2020394504-A1 · Dec 17, 2020 · US
Data Compressor Logic Circuit
US-2020389181-A1 · Dec 10, 2020 · US
Method and Apparatus for Sorting of Regions in a Vector
US-2020372099-A1 · Nov 26, 2020 · US
Method and Apparatus for Vector Sorting using Vector Permutation Logic
US-2020372098-A1 · Nov 26, 2020 · US
Method and Apparatus for Vector Based Finite Impulse Response (FIR) Filtering
US-2020373913-A1 · Nov 26, 2020 · US
Method and Apparatus for Dual Multiplication Units in a Data Path
US-2020371797-A1 · Nov 26, 2020 · US
Method and apparatus for vector sorting
US-2020371791-A1 · Nov 26, 2020 · US
Method and Apparatus for Permuting Streamed Data Elements
US-2020371799-A1 · Nov 26, 2020 · US
Method and Apparatus for Vector Based Matrix Multiplication
US-2020371798-A1 · Nov 26, 2020 · US
Method and Apparatus for Dual Issue Multiply Instructions
US-2020371786-A1 · Nov 26, 2020 · US
Method and Apparatus for Implied Bit Handling in Floating Point Multiplication
US-2020371747-A1 · Nov 26, 2020 · US
Memory device and computing device using the same
US-2020356308-A1 · Nov 12, 2020 · US
Matrix multiplier
US-2020334322-A1 · Oct 22, 2020 · US
Data compressor logic circuit
US-10756753-B2 · Aug 25, 2020 · US
Memory device and computing device using the same
US-2020257500-A1 · Aug 13, 2020 · US
Multiplication operations in memory
US-10705798-B2 · Jul 7, 2020 · US
Binary parallel adder and multiplier
US-2020210146-A1 · Jul 2, 2020 · US
Massively parallel neural inference computing elements
US-2020202205-A1 · Jun 25, 2020 · US
Signed multiplication using unsigned multiplier with dynamic fine-grained operand isolation
US-2020150924-A1 · May 14, 2020 · US
Frequently asked questions
Answers are generated from the same data shown on this page.
- What is CPC G06F7/53?
- CPC G06F7/53 is the Cooperative Patent Classification code for “in parallel-parallel fashion, i.e. both operands being entered in parallel (G06F7/533 takes precedence).”
- How many patents are filed under CPC G06F7/53 (in parallel-parallel fashion, i.e. both operands being entered in parallel (G06F7/533 takes precedence))?
- Our database includes 213 publications tagged with this CPC code.
- Is patent activity under CPC G06F7/53 growing?
- Publication counts under this code: 28 in 2024 vs 17 in 2025 (latest complete years).