Vector operations with operand base system conversion and re-conversion

Patent metadata

Field	Value
Publication number	US-9965276-B2
Application number	US-201615141786-A
Country	US
Kind code	B2
Filing date	Apr 28, 2016
Priority date	Jun 29, 2012
Publication date	May 8, 2018
Grant date	May 8, 2018

Abstract

Methods and apparatuses relating to vector operations with operand base system conversion and re-conversion are described. In one embodiment, a method includes executing a single instruction by receiving a vector element of a first input vector and a vector element of a second input vector expressed in a first base system, converting the vector elements into a second lower base system to form a converted vector element of the first input vector and a converted vector element of the second input vector, performing an operation on the converted vector element of the first input vector and the converted vector element of the second input vector to form a result, accumulating in a register a portion of the result with a portion of a result of a prior operation expressed in the second lower base system, and converting contents of the register into the first base system.

First claim

What is claimed is:

1. A method comprising:
decoding a single instruction with a hardware decoder of a hardware processor; and
executing the single instruction with a hardware execution unit of the hardware processor by:
receiving a vector element of a first input vector and a vector element of a second input vector expressed in a first base system;
converting the vector element of the first input vector and the vector element of the second input vector into a second lower base system to form a converted vector element of the first input vector and a converted vector element of the second input vector;
performing an operation on the converted vector element of the first input vector and the converted vector element of the second input vector to form a result;
accumulating in a register a portion of the result with a portion of a result of a prior operation expressed in the second lower base system; and
converting contents of the register into the first base system.

2. The method of claim 1 , wherein the executing the single instruction with the hardware execution unit of the hardware processor further comprises selecting a size of the register to store any carry over within the register.

3. The method of claim 1 , wherein the first base system corresponds to a maximum digit size of 64 bits and the second lower base system corresponds to a maximum digit size of 52 bits.

4. The method of claim 1 , wherein the contents of the register include a digit that is larger than the second lower base system's largest digit.

5. The method of claim 1 , wherein the executing further comprises iteratively performing operation and accumulation sequences to effect a complete operation on the first input vector and the second input vector.

6. The method of claim 5 , wherein the iterative operation and accumulation sequences include a shift operation that shifts elements of the first input vector to a neighboring vector element location.

7. A hardware processor comprising:
a hardware decoder to decode a single instruction; and
a hardware execution unit to execute the single instruction to:
receive a vector element of a first input vector and a vector element of a second input vector expressed in a first base system;
convert the vector element of the first input vector and the vector element of the second input vector into a second lower base system to form a converted vector element of the first input vector and a converted vector element of the second input vector;
perform an operation on the converted vector element of the first input vector and the converted vector element of the second input vector to form a result;
accumulate in a register a portion of the result with a portion of a result of a prior operation expressed in the second lower base system; and
convert contents of the register into the first base system.

8. The hardware processor of claim 7 , wherein the hardware execution unit is to execute the single instruction to select a size of the register to store any carry over within the register.

9. The hardware processor of claim 7 , wherein the first base system corresponds to a maximum digit size of 64 bits and the second lower base system corresponds to a maximum digit size of 52 bits.

10. The hardware processor of claim 7 , wherein the contents of the register include a digit that is larger than the second lower base system's largest digit.

11. The hardware processor of claim 7 , wherein the hardware execution unit is to execute the single instruction by iteratively performing operation and accumulation sequences to effect a complete operation on the first input vector and the second input vector.

12. The hardware processor of claim 11 , wherein the iterative operation and accumulation sequences include a shift operation to shift elements of the first input vector to a neighboring vector element location.

13. A non-transitory machine readable medium that stores code that when executed by a machine causes the machine to perform a method comprising:
decoding a single instruction with a hardware decoder of a hardware processor; and
executing the single instruction with a hardware execution unit of the hardware processor by:
receiving a vector element of a first input vector and a vector element of a second input vector expressed in a first base system;
converting the vector element of the first input vector and the vector element of the second input vector into a second lower base system to form a converted vector element of the first input vector and a converted vector element of the second input vector;
performing an operation on the converted vector element of the first input vector and the converted vector element of the second input vector to form a result;
accumulating in a register a portion of the result with a portion of a result of a prior operation expressed in the second lower base system; and
converting contents of the register into the first base system.

14. The non-transitory machine readable medium of claim 13 , wherein the executing the single instruction with the hardware execution unit of the hardware processor further comprises selecting a size of the register to store any carry over within the register.

15. The non-transitory machine readable medium of claim 13 , wherein the first base system corresponds to a maximum digit size of 64 bits and the second lower base system corresponds to a maximum digit size of 52 bits.

16. The non-transitory machine readable medium of claim 13 , wherein the contents of the register include a digit that is larger than the second lower base system's largest digit.

17. The non-transitory machine readable medium of claim 13 , wherein the executing further comprises iteratively performing operation and accumulation sequences to effect a complete operation on the first input vector and the second input vector.

18. The non-transitory machine readable medium of claim 17 , wherein the iterative operation and accumulation sequences include a shift operation that shifts elements of the first input vector to a neighboring vector element location.

19. A non-transitory machine readable medium that stores code that when executed by a machine causes the machine to perform a method comprising:
decoding a single instruction with a hardware decoder of a hardware processor; and
executing the single instruction with a hardware execution unit of the hardware processor by:
receiving a vector element multiplicand and a vector element multiplier expressed in a first base system;
converting the vector element multiplicand and vector element multiplier into a second lower base system to form a converted vector element multiplicand and a converted vector element multiplier;
multiplying the converted vector element multiplicand and the converted vector element multiplier to form a multiplication result;
accumulating in a register a portion of the multiplication result with a portion of a result of a prior multiplication of operands expressed in the second lower base system; and
converting contents of the register into the first base system.

20. The non-transitory machine readable medium of claim 19 , wherein the executing the single instruction with the hardware execution unit of the hardware processor further comprises selecting a size of the register to store any carry over within the register.

21. The non-transitory machine readable medium of claim 19 , wherein the first base system corresponds to a maximum digit size of 64 bits and the secon

Assignees

• Intel Corp

Inventors

• Gueron Shay
• Krasnov Vlad

Classifications

• G06F7/5443

  Sum of products (for applications thereof, see the relevant places, e.g. G06F17/10, H03H17/00) · CPC title

• G06F17/16 Primary

  Matrix or vector computation {, e.g. matrix-matrix or matrix-vector multiplication, matrix factorization (matrix transposition G06F7/78)} · CPC title

• G06F9/30098

  Register arrangements · CPC title

• G06F9/3001

  Arithmetic instructions · CPC title

• G06F9/30036 Primary

  Instructions to perform operations on packed data, e.g. vector, tile or matrix operations · CPC title