Methods And Instructions For 32-Bit Arithmetic Support Using 16-Bit Multiply And 32-Bit Addition

Patent metadata

Field	Value
Publication number	US-2017192751-A1
Application number	US-201514986349-A
Country	US
Kind code	A1
Filing date	Dec 31, 2015
Priority date	Dec 31, 2015
Publication date	Jul 6, 2017
Grant date	—

Abstract

Instructions for 32-bit arithmetic support using 16-bit multiply and 32-bit addition without a barrel shifter. Illustrative instructions include operations that include receiving a first 32-bit operand, receiving a second 32-bit operand, shifting the second 32-bit operand right 16 or 15 bits to obtain a shifted second 32-bit operand, and adding the shifted second 32-bit operand and the first 32-bit operand to generate a 32-bit sum.

First claim

What is claimed is:

1 . A tangible computer-readable medium having stored thereon an executable instruction for performing operations comprising:
receiving a first 32-bit operand; receiving a second 32-bit operand; shifting the second 32-bit operand right 16 bits to obtain a shifted second 32-bit operand; and adding the shifted second 32-bit operand and the first 32-bit operand to generate a 32-bit sum.

2 . The tangible computer-readable medium of claim 1 wherein said first 32-bit operand comprises a signed 32-bit operand.

3 . The tangible computer-readable medium of claim 1 wherein said second 32-bit operand comprises an unsigned 32-bit operand.

4 . The tangible computer-readable medium of claim 1 wherein said shifting operation further comprises filling the first 16 bit positions with zeroes after said shifting the second 32-bit operand right 16 bits to obtain said shifted second 32-bit operand.

5 . The tangible computer-readable medium of claim 1 wherein receiving the first 32-bit operand comprises retrieving said first 32-bit operand from a first register.

6 . The tangible computer-readable medium of claim 5 wherein receiving the second 32-bit operand comprises retrieving said second 32-bit operand from a second register.

7 . The tangible computer-readable medium of claim 6 wherein said executable instruction further comprises an operation of storing said 32-bit sum in a third register.

8 . The tangible computer-readable medium of claim 1 wherein said shifting operation comprises shifting the second 32-bit operand without the use of a barrel shifter.

9 . A tangible computer-readable medium having stored thereon an executable instruction for performing operations comprising:
receiving a first signed 32-bit operand; receiving a second signed 32-bit operand; shifting the second signed 32-bit operand right 15 bits and filling the first 15 bit positions with the value of the sign bit of the second signed 32-bit operand to obtain a shifted second signed 32-bit operand; and adding the shifted second signed 32-bit operand and the first signed 32-bit operand to generate a 32-bit sum.

10 . The tangible computer-readable medium of claim 9 wherein receiving the first 32-bit operand comprises retrieving said first 32-bit operand from a first register.

11 . The tangible computer-readable medium of claim 10 wherein receiving the second 32-bit operand comprises retrieving said second 32-bit operand from a second register.

12 . The tangible computer-readable medium of claim 11 wherein said executable instruction further comprises an operation of storing said 32-bit sum in a third register.

13 . The tangible computer-readable medium of claim 9 wherein said shifting operation comprises shifting the second 32-bit operand without the use of a barrel shifter.

14 . A method of performing a multiplication of a first signed 32-bit operand and a second signed 32-bit operand using 32-bit architecture, the method comprising:
performing a signed multiplication of the first 16 bits of the first signed 32-bit operand and the last 16 bits of the second signed 32-bit operand to produce a first 32-bit product; performing an unsigned multiplication of the last 16 bits of the first signed 32-bit operand and the first 16 bits of the second signed 32-bit operand to produce a second 32-bit product; adding the first 32-bit product to the second 32-bit product to generate a first 32-bit SUM; performing an unsigned multiplication of the last 16 bits of the first signed 32-bit operand and the last 16 bits of the second signed 32-bit operand to produce a third 32-bit product; shifting the third 32-bit product right 16 bits and filling the first 16 bit positions with zeroes to obtain a shifted third 32-bit product; adding the shifted third 32-bit product and the first 32-bit sum to generate a second 32-bit sum; performing a signed multiplication of the first 16 bits of the first signed 32-bit operand and the first 16 bits of the second signed 32-bit operand to produce a fourth 32-bit product; shifting the second 32-bit sum right 15 bits and filling the first 15 bit positions with the value of the sign bit of the second 32-bit sum to obtain a shifted second 32-bit sum; and adding the shifted second 32-bit sum and the fourth 32-bit product to generate a product of the first and second signed 32-bit operands.

Assignees

• Texas Instruments Inc

Inventors

• Lingam Srinivas
• Lee Seok-Jun
• Goel Manish

Classifications

• G06F7/523 Primary

  Multiplying only · CPC title

• G06F7/5324

  partitioned, i.e. using repetitively a smaller parallel parallel multiplier or using an array of such smaller multipliers · CPC title

• G06F7/50

  Adding; Subtracting (G06F7/483 - G06F7/491, G06F7/544 - G06F7/556 take precedence) · CPC title