Multi-layer gate dielectric field-effect transistor and manufacturing process thereof

Patent metadata

Field	Value
Publication number	US-9368737-B2
Application number	US-201113877441-A
Country	US
Kind code	B2
Filing date	Oct 5, 2011
Priority date	Oct 7, 2010
Publication date	Jun 14, 2016
Grant date	Jun 14, 2016

Abstract

A field-effect transistor includes a gate, a source and a drain; a semiconductor layer between the source and the drain; and a gate insulator between the gate and the semiconductor layer. The gate insulator comprises a first layer adjoining the semiconductor layer; and a second layer. The first layer is formed from an amorphous fluoropolymer having a first dielectric constant and a first thickness. The second layer has a second dielectric constant and a second thickness. The first dielectric constant is smaller than 3, the first thickness is smaller than 200 nm, the second dielectric constant is higher than 5, and the second thickness is smaller than 500 nm.

First claim

The invention claimed is:

1. A field-effect transistor having operational stability comprising:
a gate, a source and a drain;
a semiconductor layer between the source and the drain; and
a gate insulator between the gate and the semiconductor layer;
wherein the gate insulator comprises:
a first layer adjoining the semiconductor layer at an interface, the first layer comprising a fluoropolymer; and
a second layer comprising Al 2 O 3 , the second layer deposited by atomic layer deposition (ALD) to provide increased operational stability compared to other field-effect transistors;
the first layer having a first dielectric constant and a first thickness; wherein interfacial charge trapping at the interface causes a first effect on a current between the drain and the source over time under a continuous bias stress;
the second layer having a second dielectric constant and a second thickness, the second dielectric constant being higher than the first dielectric constant; wherein a change in the polarizability of the second layer over time under continuous bias stress causes a second effect on the current between the drain and the source; and
wherein selection of the first and second thickness and the first and second dielectric constant are such that the first effect compensates at least partly the second effect which provides the increased operational stability, such that variation of the current between the source and the drain under the continuous bias stress for a period of one hour is less than 5 percent.

2. The field-effect transistor of claim 1 , wherein the variation in the current between the source and the drain under the continuous bias stress for a period of two hours is less than 5 percent.

3. The field-effect transistor of claim 1 , wherein the first layer is formed from an amorphous fluoropolymer having a glass transition temperature above 80 degrees Celcius and the fluoropolymer is selected from the group consisting of: a copolymer of 4,5-difluoro-2,2-bis(trifluoromethyl)-1,3-dioxole (PDD) and tetrafluoroethylene (TFE), or a copolymer of 2,2,4-trifluoro-5-trifluoromethoxy-1,3-dioxole (TTD) and tetrafluoroethylene (TFE).

4. The field-effect transistor of claim 3 , wherein the second layer consists of Al 2 O 3 .

5. The field-effect transistor of claim 1 , wherein the thickness of the first layer is less than 200 nm.

6. The field-effect transistor of claim 1 , wherein the thickness of the second layer is less than 500 nm.

7. The field-effect transistor of claim 1 , wherein the thickness of the first layer is less than 200 nm and the thickness of the second layer is less than 100 nm.

8. A process for manufacturing a field-effect transistor having operational stability, the process comprising:
providing a source, a drain, a gate, a semiconductor layer between the source and the drain, and a gate insulator between the gate and the semiconductor layer;
wherein providing the gate insulator comprises:
depositing a first layer comprising a fluoropolymer, wherein the first layer has a first dielectric constant and a first thickness, the first layer defining an interface with the semiconductor layer; wherein the depositing of the first layer is such that interfacial charge trapping at the interface causes a first effect on a current between the source and drain over time under a continuous bias stress; and
depositing a second layer comprising Al 2 O 3 , wherein the second layer is deposited by atomic layer deposition (ALD), the second layer having a second dielectric constant and a second thickness, the second dielectric constant being higher than the first dielectric constant; wherein a change in the polarizability of the second layer over time under continuous bias stress causes a second effect on the current between the drain and the source; and
wherein selection of the first and second thickness and the first and second dielectric constant are such that the first effect compensates at least partly the second effect to thereby provide increased operational stability compared to other field-effect transistors.

9. The field-effect transistor of claim 1 , wherein the first layer is an amorphous fluoropolymer having a glass transition temperature above 80 degrees Celsius selected from the group consisting of: a copolymer of fluorinated 1,3-dioxole and tetrafluoroethylene (TFE), a copolymer of perfluorofuran (PFF) and tetrafluoroethylene (TFE), a homo- or copolymer of perfluoro(4-vinyloxyl)-1-alkenes, and combinations thereof.

10. The field-effect transistor of claim 1 , wherein the second layer further comprises an inorganic material selected from the group consisting of SiN x , TiO 2 , HfO 2 , Ta 2 O 5 , SiO 2 , Y 2 O 3 , ZrO 2 , and combinations thereof.

11. The field-effect transistor of claim 1 , wherein the variation of the current between the source and the drain, normalized to the initial current at the end of a direct current (DC) bias test for a period of one hour, is less than 0.03 per hour.

12. The field-effect transistor of claim 1 , wherein the thickness of the first layer is less than 50 nm and the thickness of the second layer is about 50 nm or less.

13. The field-effect transistor of claim 1 , wherein the thickness of the first layer is less than 100 nm.

14. The process of claim 8 , wherein the thickness of the first layer is less than 200 nm.

15. The process of claim 8 , wherein the thickness of the second layer is less than 500 nm.

16. The process of claim 15 , wherein the thickness of the first layer is less than 200 nm and the thickness of the second layer is less than 100 nm.

17. The process of claim 8 , wherein the second layer consists of Al 2 O 3 .

18. The process of claim 8 , wherein the thickness of the first layer is less than 50 nm and the thickness of the second layer is about 50 nm or less.

Assignees

• Hwang Do Kyung
• Kim Jungbae
• Fuentes-Hernandez Canek
• Kippelen Bernard
• Georgia Tech Res Inst

Inventors

• Hwang Do Kyung
• Kim Jungbae
• Fuentes-Hernandez Canek
• Kippelen Bernard

Classifications

• H10D86/423

  comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO · CPC title

• H10D86/60

  wherein the TFTs are in active matrices · CPC title

• H01L51/0071

  Electricity · mapped topic

• H01L51/0545

  Electricity · mapped topic

• H01L51/0533

  Electricity · mapped topic