Thin film transistor, method of manufacturing the same, display substrate and display apparatus

Patent metadata

Field	Value
Publication number	US-9478665-B2
Application number	US-201414768992-A
Country	US
Kind code	B2
Filing date	Nov 27, 2014
Priority date	Jul 22, 2014
Publication date	Oct 25, 2016
Grant date	Oct 25, 2016

Abstract

A thin film transistor is disclosed in the present invention. The thin film transistor comprises: a substrate, an active layer, a first etching barrier layer, a second etching barrier layer, a source and a drain, wherein: the active layer is disposed over the substrate; the first etching barrier layer is disposed over the active layer; the second etching barrier layer is disposed over the first etching barrier layer; the source and the drain are disposed over the second etching barrier layer, and are connected to each other through the active layer by means of via holes formed in the first etching barrier layer and the second etching barrier layer by etching; and a length of the first etching barrier layer at a channel position is less than a length of the second etching barrier layer. A method of manufacturing the thin film transistor, an array substrate and a display apparatus are also disclosed in the present invention. A length of a channel of the thin film transistor according to the present invention is less than the length of the channel of the conventional thin film transistor. Thereby, size and energy consumption of the thin film transistor are reduced, an aperture ratio of a liquid crystal panel is increased, and a turn-on current of the thin film transistor is increased, so that whole performance of the thin film transistor is further improved.

First claim

What is claimed is:

1. A thin film transistor comprising: a substrate, an active layer, a first etching barrier layer, a second etching barrier layer, a source and a drain, wherein:
the active layer is disposed over the substrate;
the first etching barrier layer is disposed over the active layer;
the second etching barrier layer is disposed over the first etching barrier layer;
the source and the drain are disposed over the second etching barrier layer, and are connected to each other through the active layer by means of via holes which are formed in the first etching barrier layer and the second etching barrier layer by etching; and
a length of the first etching barrier layer at a channel position is less than a length of the second etching barrier layer at the channel position.

2. The thin film transistor of claim 1 , wherein:
the first etching barrier layer has a greater etch rate than the second etching barrier layer.

3. The thin film transistor of claim 1 , wherein:
a deposition rate for forming the first etching barrier layer is greater than that for the second etching barrier layer.

4. The thin film transistor of claim 1 , wherein:
both the first etching barrier layer and the second etching barrier layer are made of silicon oxide; or the first etching barrier layer is made of silicon nitride while the second etching barrier layer is made of silicon oxide.

5. The thin film transistor of claim 1 , further comprising:
a passivation layer disposed over the source and the drain.

6. The thin film transistor of claim 1 , wherein:
the active layer is made of metal oxide semiconductor material.

7. The thin film transistor of claim 1 , wherein:
the via holes are formed in the first etching barrier layer and the second etching barrier layer through a single etching process.

8. An array substrate comprising the thin film transistor according to claim 1 .

9. The thin film transistor of claim 2 , wherein:
the via holes are formed in the first etching barrier layer and the second etching barrier layer through a single etching process.

10. A method of manufacturing a thin film transistor comprising:
forming a semiconductor layer over a substrate and patterning the semiconductor layer so as to obtain an active layer;
forming a first etching barrier material layer on the active layer;
forming a second etching barrier material layer on the first etching barrier material layer;
forming, by etching, via holes in the first etching barrier layer and the second etching barrier layer such that a length of the first etching barrier layer at a channel position is less than a length of the second etching barrier layer at the channel position; and
forming an electrode material layer on the second etching barrier layer, and patterning the electrode material layer so as to obtain a source and a drain, wherein the source and the drain are connected to each other through the active layer by means of the via holes formed in the first etching barrier layer and the second etching barrier layer.

11. The method of claim 10 , wherein:
the first etching barrier layer has a greater etch rate than the second etching barrier layer.

12. The method of claim 10 , wherein:
a deposition rate for forming the first etching barrier layer is greater than that for the second etching barrier layer.

13. The method of claim 10 , wherein:
both the first etching barrier material layer and the second etching barrier material layer are made of silicon oxide; or the first etching barrier layer is made of silicon nitride while the second etching barrier layer is made of silicon oxide.

14. The method of claim 10 , wherein:
the active layer is made of metal oxide semiconductor material.

15. The method of claim 10 , further comprising a step of forming a passivation layer on the source and the drain after the source and the drain are formed.

16. The method of claim 10 , wherein:
the via holes are formed in the first etching barrier layer and the second etching barrier layer through a single etching process.

17. The method of claim 12 , wherein:
both the first etching barrier layer and the second etching barrier layer are made of silicon oxide; or the first etching barrier layer is made of silicon nitride while the second etching barrier layer is made of silicon oxide.

Assignees

• Boe Technology Group Co Ltd

Inventors

• Zhang Feng
• Cao Zhanfeng
• Yao Qi

Classifications

• H10W20/076

  in via holes or trenches · CPC title

• H10W20/074

  of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers · CPC title

• H10W20/071

  of dielectric parts thereof · CPC title

• H10D99/00

  Subject matter not provided for in other groups of this subclass · CPC title

• H10D86/423

  comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO · CPC title