Electrical signal conversion with reduced-distance element rotation

Patent metadata

Field	Value
Publication number	US-9350371-B2
Application number	US-201414571274-A
Country	US
Kind code	B2
Filing date	Dec 15, 2014
Priority date	May 30, 2013
Publication date	May 24, 2016
Grant date	May 24, 2016

Abstract

In one aspect, an electrical signal converter is disclosed. The exemplary electrical signal converter may include a plurality of ordered converter elements. Element selection logic may be provided to pseudorandomly select a pointer to a switch matrix, wherein the switch matrix maps converter elements according to a stepwise “delta-two-maximum pattern.” Advantageously, pseudorandom stepwise delta-two-maximum patterns may be applied both to a first order converter, and to a feedback converter for error correction.

First claim

What is claimed is:

1. An electrical signal converter, comprising:
an input for receiving a first species of signal;
at least four discrete converter elements for converting the first species of signal into a second species of signal, wherein the converter elements are arranged in an array;
a switch for mapping the input to the converter elements; and
logic configured to cause the switch to:
on a first cycle, use a first converter element at a first position to convert the input; and
on a second cycle, use a second converter element at a second position to convert the input, wherein the second position is no more than two positions away from the first position.

2. The electrical signal converter of claim 1 , wherein the converter elements are digital-to-analog converter elements.

3. The electrical signal converter of claim 2 , comprising a plurality of inputs, and wherein the plurality of inputs form a thermometer code.

4. The electrical signal converter of claim 1 , wherein the converter elements are analog-to-digital converters.

5. The electrical signal converter of claim 4 , wherein the second species of signal comprises a thermometer code.

6. The electrical signal converter of claim 1 , wherein the logic is configured to select the second position according to a pseudorandom input.

7. The electrical signal converter of claim 1 , wherein the logic is configured to select the second position according to a pseudorandom input plus a constant.

8. The electrical signal converter of claim 1 , wherein the first position is k, the second position is k t+1 , and wherein selecting k t+1 comprises:
if k is even, k t+1 =2; and if k is odd, k t+1 =k−2.

9. The electrical signal converter of claim 8 , wherein selecting k t+1 further comprises:
if k==1, k t+1 =2; and if k is even and k==n, k t+1 =k−1.

10. The electrical signal converter of claim 1 , wherein the first position is k, the second position is k t+1 , and wherein selecting k t+1 comprises swapping k and k+1.

11. The electrical signal converter of claim 1 comprising exactly n converter elements, wherein the first position is k, the second position is k t+1 , and wherein selecting k t+1 comprises:
on even cycles, if k is odd and k≠n, swap k and k+1;
on odd cycles, if k is even and k≠n, swap k and k+1.

12. A delta-sigma modulator comprising:
an analog-to-digital converter configured to receive an analog input and provide a digital output, the analog-to-digital converter comprising a plurality of n ordered converter elements, wherein n>3, and logic to rotate converter elements according to a first stepwise pattern wherein at a step, each converter element is switched to a position not more than two positions from its previous position;
a digital-to-analog converter configured to receive the digital output of the analog-to-digital converter and provide an analog output, the digital-to-analog converter comprising a plurality of ordered converter elements and logic to rotate converter elements according to a second stepwise pattern wherein at a step, each converter element is switched to a position not more than two positions from its previous position;
a loop filter configured to receive the analog input and the analog output of the digital-to-analog converter, and to provide a filtered analog signal the analog-to-digital converter; and
element selection logic configured to select a number of steps;
wherein the first stepwise pattern and second stepwise pattern each ensure that a converter element used at a position k on a first conversion cycle is used at k t+1 on a second conversion cycle, wherein |k−k t+1 |≦2.

13. The delta-sigma modulator of claim 12 , wherein:
at least one of the stepwise patterns comprises, for element k, if k is of a first species, k t+1 =k+2; if k is of a second species, k t+1 =k−2.

14. The delta-sigma modulator of claim 12 , wherein:
the digital-to-analog converter comprises n converter elements;
the second pattern comprises two cycles, wherein, for element k:
on the first cycle, if k is odd, swap k and k+1;
on the second cycle, if k is even, swap k and k+1.

15. The delta-sigma modulator of claim 12 , wherein the element selection logic selects the number of steps by calculating a pseudorandom number plus a constant.

16. A method performed by an electrical signal converter, comprising:
during a first time period, selecting a first converter element from among a plurality of n available ordered converter elements in an electrical signal converter, wherein n>3;
during a second time period:
calculating a pseudorandom number;
selecting a second converter element by stepping through available converter elements according to a stepwise pattern, wherein the number of steps is a function of the pseudorandom number and is less than two.

17. The method of claim 16 , wherein the function of the pseudorandom number includes addition of a constant.

18. The method of claim 17 , wherein the constant is one.

19. The method of claim 16 , wherein stepwise pattern includes the steps 1-2-4-6-8 and 7-5-3-1.

20. The method of claim 16 , wherein the stepwise pattern comprises shifting converter elements up or down two elements.

21. The method of claim 16 , wherein the stepwise pattern comprises swapping adjacent converter elements.

22. The method of claim 16 , wherein the stepwise pattern comprises:
for element k, if k is of a first species, k t+1 −k+2; if k is of a second species, select k t+1 =k−2.

23. The method of claim 16 , wherein:
the stepwise pattern comprises two cycles, wherein, for element k:
on the first cycle, for a first species of k, swap k and k+1;
on the second cycle, for a second species of k, swap k and k+1.

Assignees

• Analog Devices Global

Inventors

• Caldwell Trevor Clifford
• Schreier Richard E
• Alldred David
• Yang Wenhua W

Classifications

• H03M3/464

  Details of the digital/analogue conversion in the feedback path · CPC title

• H03M1/361

  having a separate comparator and reference value for each quantisation level, i.e. full flash converter type · CPC title

• H03M1/0673 Primary

  using random selection of the elements (with data-controlled random generator H03M1/0665) · CPC title

• H03M3/338

  by permutation in the time domain, e.g. dynamic element matching (in multiple bit sub-converters H03M1/066) · CPC title

• H03M3/30

  Delta-sigma modulation · CPC title