Background flash offset calibration in continuous-time delta-sigma ADCS

Patent metadata

Field	Value
Publication number	US-9843337-B1
Application number	US-201715460433-A
Country	US
Kind code	B1
Filing date	Mar 16, 2017
Priority date	Mar 16, 2017
Publication date	Dec 12, 2017
Grant date	Dec 12, 2017

Abstract

Analog-to-digital converters (ADCs) can be used inside ADC architectures, such as delta-sigma ADCs. The error in such internal ADCs can degrade performance. To calibrate the errors in an internal ADC, comparator offsets of the internal ADC can be estimated by computing a mean of each comparator of the internal ADC. Relative differences in the computed means serves as estimates for comparator offsets. If signal paths in the internal ADC are shuffled, the estimation of comparator offsets can be performed in the background without interrupting normal operation. Shuffling of signal paths may introduce systematic measurement errors, which can be measured and reversed to improve the estimation of comparator offsets.

First claim

What is claimed is:

1. A method for calibrating an internal analog-to-digital converter, the method comprising:
shuffling signal paths of an internal analog-to-digital converter;
generating comparator outputs by the internal analog-to-digital converter;
measuring mean values of respective comparator outputs in the internal analog-to-digital converter; and
estimating comparator offsets based on the measured mean values.

2. The method of claim 1 , wherein measuring the mean values of respective comparator outputs comprises accumulating samples of a given comparator output to obtain a given mean value of the given comparator output.

3. The method of claim 1 , wherein estimating comparator offsets comprises determining relative differences between the measured mean values.

4. The method of claim 1 , further comprising:
determining an impulse response matrix corresponding to the shuffling of the signal paths;
wherein estimating comparator offsets includes applying an inverse of the impulse response matrix to the measured mean values prior to determining the comparator offsets.

5. The method of claim 1 , further comprising:
adjusting comparators of the internal analog-to-digital converter based on the estimated comparator offsets.

6. The method of claim 1 , wherein shuffling signal paths of the internal analog-to-digital converter comprises shuffling reference voltages provided to comparators of the internal analog-to-digital converter.

7. The method of claim 1 , wherein shuffling signal paths of the internal analog-to-digital converter ensures that comparators of the internal analog-to-digital converter experience substantially a same number of transitions over time.

8. The method of claim 1 , further comprising:
disconnecting an input of an analog-to-digital converter having the internal analog-to-digital converter prior to the generating the comparator outputs.

9. The method of claim 1 , wherein measuring the mean values of respective comparator outputs comprises measuring a sum of samples of a given comparator output.

10. The method of claim 1 , wherein:
the shuffling and the generating are performed while an input signal is provided to an input of an analog-to-digital converter having the internal analog-to-digital converter.

11. A calibration system for an internal analog-to-digital converter, the calibration system comprising:
one or more averaging blocks for computing mean values for respective comparator outputs in the internal analog-to-digital converter, wherein the internal analog-to-digital converter has signal paths which are shuffled; and
a calibration block for determining offset calibration codes based on the mean values computed by the one or more averaging blocks, wherein the offset calibration codes are usable to adjust comparator offsets in the internal analog-to-digital converter.

12. The calibration system of claim 11 , wherein the calibration block determines offset calibration codes based on relative differences between the mean values.

13. The calibration system of claim 11 , further comprising:
circuitry for forcing comparators which are not under test to output a static value while a comparator under test is being measured.

14. The calibration system of claim 11 , wherein the calibration block further determines an impulse response matrix corresponding to a shuffler which shuffles the signal paths and applies an inverse of the impulse response matrix to the mean values prior to determining the offset calibration codes.

15. The calibration system of claim 11 , wherein the offset calibration codes control reference correction currents, wherein each reference correction current changes an average comparator output.

16. The calibration system of claim 11 , wherein the one or more averaging blocks comprises one or more of the following: a digital counter, a digital adder, and an accumulator.

17. The calibration system of claim 11 , wherein the calibration block is implemented in a programmable microprocessor embedded on-chip with an analog-to-digital converter having the internal analog-to-digital converter configured to execute instructions that determines the offset calibration codes.

18. The calibration system of claim 11 , wherein the one or more averaging blocks and the calibration block are implemented as digital logic on-chip with an analog-to-digital converter having the internal analog-to-digital converter.

19. A delta-sigma modulator having offset calibration, the delta-sigma modulator comprising:
an internal analog-to-digital converter for generating comparator outputs based on reference voltages provided to respective comparators and an analog signal from a loop filter;
means for shuffling the reference voltages of the internal analog-to-digital converter;
means for computing average values of respective comparator outputs of the internal analog-to-digital converter;
means for estimating offsets of the respective comparators in the internal analog-to-digital converter based on relative differences between the average values; and
means for correcting offsets of the respective comparators based on the estimated offsets.

20. The delta-sigma modulator of claim 19 , further comprising:
means for determining an impulse response matrix of the means for shuffling the reference voltages;
wherein the means for estimating offsets of the comparators takes into account the impulse response matrix.

Assignees

• Analog Devices Global

Inventors

• Li Zhao
• Caldwell Trevor Clifford
• Alldred David Nelson
• Dong Yunzhi
• Shrestha Prawal Man
• Zhao Jialin
• Shibata Hajime
• Kozlov Victor
• Schreier Richard E
• Yang Wenhua W

Classifications

• H03M1/12

  Analogue/digital converters ({H03M1/001 – } H03M1/10 take precedence) · CPC title

• H03M3/464

  Details of the digital/analogue conversion in the feedback path · CPC title

• H03M1/1023 Primary

  Offset correction (H03M1/1019 takes precedence; removal of offset already present on the analogue input signal H03M1/1295) · CPC title

• H03M1/1009

  Calibration · CPC title

• H03M3/384

  Offset correction (removal of offset already present on the analogue input signal H03M3/494) · CPC title