System for conversion between analog domain and digital domain with mismatch error shaping

Patent metadata

Field	Value
Publication number	US-9787316-B2
Application number	US-201615246580-A
Country	US
Kind code	B2
Filing date	Aug 25, 2016
Priority date	Sep 14, 2015
Publication date	Oct 10, 2017
Grant date	Oct 10, 2017

Abstract

The invention provides a system for conversion between analog domain and digital domain with mismatch error shaping, including a DAC, a first injection circuit coupled to the DAC, and a second injection circuit coupled to the DAC. The DAC generates a first analog value in response to a first digital value, and generates a second analog value in response to a second digital value. The first injection circuit enables an analog injection value to be injected to the second analog value when the DAC generates the second analog value, wherein the analog injection value is converted from a digital injection value formed by a subset of bits of the first digital value. The second injection circuit injects the digital injection value to the second digital value, or combines the digital injection value and a related value obtained according to the second analog value.

First claim

What is claimed is:

1. A system for conversion between analog domain and digital domain with mismatch error shaping, receiving a first input analog value and outputting a first output digital value converted from the first input analog value during a first cycle, and receiving a second input analog value and outputting a second output digital value converted from the second input analog value during a second cycle, and comprising:
a DAC (digital-to-analog converter) generating a first analog value in response to a first digital value, and generating a second analog value in response to a second digital value;
a first injection circuit coupled to the DAC, enabling an analog injection value to be injected to the second analog value when the DAC generates the second analog value, wherein the analog injection value is converted from a digital injection value formed by a subset of bits of the first digital value, and
a second injection circuit coupled to the DAC, for injecting the digital injection value to the second digital value; and
a register,
wherein the first injection circuit comprises an additional control circuit coupled to the register, and the DAC comprises:
a peripheral circuit coupled to the register; and
a plurality of capacitors, each of the capacitors having a top terminal coupled to a common node, and a bottom terminal coupled to the peripheral circuit,
wherein during a first phase of the second cycle, the additional control circuit controls the register to register the subset of bits of the first digital value, and controls the peripheral circuit to conduct the bottom terminals of the capacitors to voltages reflecting the subset of bits of the first digital value, and to conduct the common node to the second input analog value, so as to enable the analog injection value to be injected, and
during a second phase of the second cycle after the first phase, the peripheral circuit conducts the bottom terminals of the capacitors to a reset voltage, and the register resets.

2. The system of claim 1 further comprising:
a comparator coupled to the common node and the register, wherein during a period of the second cycle, the comparator compares a voltage at the common node to set a bit of the register.

3. The system of claim 1 further comprising:
a second register,
a DEM (dynamic element matching) circuit coupled to the second register,
a second peripheral circuit coupled to the DEM circuit, and
a plurality of second capacitors, each of the second capacitors having a top terminal coupled to the common node, and a bottom terminal coupled to the second peripheral circuit;
wherein during the first phase and the second phase of the second cycle, the second peripheral circuit conducts the bottom terminals of the second capacitors to the reset voltage, and
during a third phase of the second cycle, the DEM circuit selects a number of the second capacitors with the number reflecting bits registered by the second register, and the second peripheral circuit conducts the bottom terminals of the selected second capacitors to a setting voltage.

4. A system for conversion between analog domain and digital domain with mismatch error shaping, comprising:
a DAC generating a first analog value in response to a first digital value during a first cycle, and generating a second analog value in response to a second digital value during a second cycle; wherein the system receives an input digital value and outputs an output analog value during the second cycle, and the second digital value is formed by a second subset of the bits of a combined value,
a first injection circuit coupled to the DAC, enabling an analog injection value to be injected to the second analog value when the DAC generates the second analog value, wherein the analog injection value is converted from a digital injection value formed by a subset of bits of the first digital value, and the first injection circuit sequentially loads the digital injection value and the second digital value to the DAC during different periods of the second cycle, so as to enable the analog injection value to be injected;
a second injection circuit coupled to the DAC, for combining the digital injection value and the input digital value to form the combined value;
a second DAC,
a DEM circuit coupled between the second injection circuit and the second DAC, for receiving an internal digital value formed by a first subset of bits of the combined value, coding the internal digital value from binary code to thermometer code, and accordingly controlling the second DAC to synthesize an internal analog value, and
a sum block coupled between the DAC and the second DAC for combining the internal analog value and the second analog value to form the output analog value.

5. A system for conversion between analog domain and digital domain with mismatch error shaping, comprising:
a DAC generating a first analog value in response to a first digital value, and generating a second analog value in response to a second digital value;
a first injection circuit coupled to the DAC, enabling an analog injection value to be injected to the second analog value when the DAC generates the second analog value, wherein the analog injection value is converted from a digital injection value formed by a subset of bits of the first digital value;
a second injection circuit coupled to the DAC, for combining the digital injection value and a related value obtained according to the second analog value;
a second DAC coupled to the first injection circuit, and
a sum block coupled to the DAC and the second DAC,
wherein the first injection circuit comprises an operator coupled between a first port and a second port;
during a first cycle, the operator provides the digital injection value via the second port, the second digital value is received via the first port, the first injection circuit routes the second port to the second DAC to convert the digital injection value to the analog injection value, and routes the first port to the DAC to convert the second digital value to the second analog value, so as to enable the analog injection value to be injected to the second analog value by the sum block which combines the analog injection value and the second analog value.

6. The system of claim 5 , wherein during a second cycle, the operator provides a second digital injection value via the second port, a subsequent digital value is received via the first port, the first injection circuit routes the second port to the DAC to convert the second digital injection value to a second analog injection value, and routes the first port to the second DAC to convert the subsequent digital value to a subsequent analog value, so as to enable the second analog injection value to be injected to the subsequent analog value by the sum block which combines the second analog injection value and the subsequent analog value, wherein the second digital injection value is formed by a subset of bits of the second digital value.

7. A system for conversion between analog domain and digital domain with mismatch error shaping, comprising:
a DAC generating a first analog value in response to a first digital value, and generating a second analog value in response to a second digital value;
a first injection circuit coupled to the DAC, enabling an analog injection value to be injected to the second analog value when the DAC generates the second analog value, wherein the analog injection value is converted from a digital injection value formed by a subset of bits of the first digital value;
a second injection circuit coupled to the DAC, for combining the digital injection value and a related value obtained according to the second analog value;
a second DAC coupled to the first injection c

Assignees

• Mediatek Inc

Inventors

• Shu Yun-Shiang

Classifications

• H03M1/145

  the steps being performed sequentially in series-connected stages (H03M1/141, H03M1/143, H03M1/16 take precedence) · CPC title

• H03M1/0673 Primary

  using random selection of the elements (with data-controlled random generator H03M1/0665) · CPC title

• H03M1/68

  with conversions of different sensitivity, i.e. one conversion relating to the more significant digital bits and another conversion to the less significant bits · CPC title

• H03M3/338 Primary

  by permutation in the time domain, e.g. dynamic element matching (in multiple bit sub-converters H03M1/066) · CPC title

• H03M3/344

  by filtering other than the noise-shaping inherent to delta-sigma modulators, e.g. anti-aliasing · CPC title