System for conversion between analog domain and digital domain with mismatch error shaping

Patent metadata

Field	Value
Publication number	US-9831885-B2
Application number	US-201715497240-A
Country	US
Kind code	B2
Filing date	Apr 26, 2017
Priority date	Sep 14, 2015
Publication date	Nov 28, 2017
Grant date	Nov 28, 2017

Abstract

The invention provides a system for conversion between analog domain and digital domain with mismatch error shaping, including a DAC, a first injection circuit coupled to the DAC, and a second injection circuit coupled to the DAC. The DAC generates a first analog value in response to a first digital value, and generates a second analog value in response to a second digital value. The first injection circuit enables an analog injection value to be injected to the second analog value when the DAC generates the second analog value, wherein the analog injection value is converted from a digital injection value formed by a subset of bits of the first digital value. The second injection circuit injects the digital injection value to the second digital value, or combines the digital injection value and a related value obtained according to the second analog value.

First claim

What is claimed is:

1. A system for conversion between analog domain and digital domain with mismatch error shaping, comprising:
a DAC (digital-to-analog converter) for generating a second analog value at an associated terminal by digital-to-analog converting a second digital value during a current cycle;
a first injection circuit coupled to the DAC, enabling an analog injection value to be injected to the second analog value during the current cycle, wherein the analog injection value is converted from a digital injection value formed by a subset of bits of a first digital value; the second digital value and the first digital value are samples of a same associated sequence respectively at the current cycle and an earlier cycle before the current cycle, and the first digital value is digital-to-analog converted during the earlier cycle for generating a first analog value at the same associated terminal before the second analog value; and
a second injection circuit coupled to the DAC, for one of the following: injecting the digital injection value to the second digital value, and combining the digital injection value and a related value obtained according to the second analog value.

2. The system of claim 1 further comprising:
a first ADC (analog-to-digital converter) for converting an input analog value to a converted input digital value,
a first sum block coupled between the input analog value and the DAC for subtracting the second analog value from the input analog value to form an internal analog value,
a second ADC coupled to the first sum block for converting the internal analog value to an internal digital value, and
a second sum block coupled to the first ADC and the second ADC for combining the second digital value and the internal digital value.

3. The system of claim 2 , wherein the second injection circuit is coupled between the first ADC and the DAC, and is arranged to inject the digital injection value to the second digital value by combining the converted input digital value and the digital injection value to form the second digital value.

4. The system of claim 2 , wherein the second digital value is the converted input digital value, the second injection circuit is arranged to combine the digital injection value and the related value which is the internal digital value, and the second injection circuits is implemented by the second sum block.

5. The system of claim 1 receiving a first input analog value and outputting a first output digital value converted from the first input analog value during the earlier cycle, and receiving a second input analog value and outputting a second output digital value converted from the second input analog value during the current cycle, wherein the system further comprises a register, the first injection circuit comprises an additional control circuit coupled to the register, and the DAC comprises:
a peripheral circuit coupled to the register; and
a plurality of capacitors, each of the capacitors having a top terminal coupled to a common node, and a bottom terminal coupled to the peripheral circuit,
wherein during a first phase of the current cycle, the additional control circuit controls the register to register the subset of bits of the first digital value, and controls the peripheral circuit to conduct the bottom terminals of the capacitors to voltages reflecting the subset of bits of the first digital value, and to conduct the common node to the second input analog value, so as to enable the analog injection value to be injected, and
during a second phase of the current cycle after the first phase, the peripheral circuit conducts the bottom terminals of the capacitors to a reset voltage, and the register resets.

6. The system of claim 5 further comprising:
a comparator coupled to the common node and the register, wherein during a period of the current cycle, the comparator compares a voltage at the common node to set a bit of the register.

7. The system of claim 5 further comprising:
a second register,
a DEM (dynamic element matching) circuit coupled to the second register,
a second peripheral circuit coupled to the DEM circuit, and
a plurality of second capacitors, each of the second capacitors having a top terminal coupled to the common node, and a bottom terminal coupled to the second peripheral circuit;
wherein during the first phase and the second phase of the current cycle, the second peripheral circuit conducts the bottom terminals of the second capacitors to the reset voltage, and
during a third phase of the current cycle, the DEM circuit selects a number of the second capacitors with the number reflecting bits registered by the second register, and the second peripheral circuit conducts the bottom terminals of the selected second capacitors to a setting voltage.

8. The system of claim 1 , wherein the first injection circuit sequentially loads the digital injection value and the second digital value to the DAC during different periods of the current cycle, so as to enable the analog injection value to be injected.

9. The system of claim 8 receiving an input digital value and outputting an output analog value during the current cycle, wherein the second injection circuit is arranged to inject the digital injection value to the second digital value by combining the input digital value and the digital injection value to form a combined value, the second digital value is formed by a second subset of the bits of the combined value, and the system further comprises:
a second DAC,
a DEM circuit coupled between the second injection circuit and the second DAC, for receiving an internal digital value formed by a first subset of bits of the combined value, coding the internal digital value from binary code to thermometer code, and accordingly controlling the second DAC to synthesize an internal analog value, and
a sum block coupled between the DAC and the second DAC for combining the internal analog value and the second analog value to form the output analog value.

10. The system of claim 1 further comprising:
a second DAC coupled to the first injection circuit, and
a sum block coupled to the DAC and the second DAC,
wherein the first injection circuit comprises an operator coupled between a first port and a second port;
during the current cycle, the operator provides the digital injection value via the second port, the second digital value is received via the first port, the first injection circuit routes the second port to the second DAC to convert the digital injection value to the analog injection value, and routes the first port to the DAC to convert the second digital value to the second analog value, so as to enable the analog injection value to be injected to the second analog value by the sum block which combines the analog injection value and the second analog value.

11. The system of claim 10 , wherein during a subsequent cycle after the current cycle, the operator provides a second digital injection value via the second port, a subsequent digital value is received via the first port, the first injection circuit routes the second port to the DAC to convert the second digital injection value to a second analog injection value, and routes the first port to the second DAC to convert the subsequent digital value to a subsequent analog value, so as to enable the second analog injection value to be injected to the subsequent analog value by the sum block which combines the second analog injection value and the subsequent analog value, wherein the second digital injection value is formed by a subset of bits of the second digital value.

12. The system of claim 1 further comprising:
a second D

Assignees

• Mediatek Inc

Inventors

• Shu Yun-Shiang

Classifications

• H03M1/001

  Analogue/digital/analogue conversion · CPC title

• H03M1/066 Primary

  by continuously permuting the elements used, i.e. dynamic element matching · CPC title

• H03M3/338 Primary

  by permutation in the time domain, e.g. dynamic element matching (in multiple bit sub-converters H03M1/066) · CPC title

• H03M3/344

  by filtering other than the noise-shaping inherent to delta-sigma modulators, e.g. anti-aliasing · CPC title

• H03M1/68

  with conversions of different sensitivity, i.e. one conversion relating to the more significant digital bits and another conversion to the less significant bits · CPC title