Bi-directional ESD diode structure with ultra-low capacitance that consumes a small amount of silicon real estate

Patent metadata

Field	Value
Publication number	US-9337299-B2
Application number	US-201514709588-A
Country	US
Kind code	B2
Filing date	May 12, 2015
Priority date	Jun 30, 2013
Publication date	May 10, 2016
Grant date	May 10, 2016

Abstract

A bi-directional electrostatic discharge diode structure consumes substantially less silicon real estate and provides ultra-low capacitance by utilizing a p− epitaxial layer that touches and lies between an n+ lower epitaxial layer and an n+ upper epitaxial layer. A metal contact touches and lies over a p+ layer, which touches and lies over the n+ upper epitaxial layer.

First claim

What is claimed is:

1. A method of forming a diode structure comprising:
epitaxially growing a first semiconductor layer on a substrate region, the substrate region having a first conductivity type and a dopant concentration, the first semiconductor layer having a second conductivity type and a dopant concentration;
epitaxially growing a second semiconductor layer on the first semiconductor layer, the second semiconductor layer having the first conductivity type and a dopant concentration that is substantially less than the dopant concentration of the substrate region;
epitaxially growing a third semiconductor layer on the second semiconductor layer, the third semiconductor layer having the second conductivity type; and
implanting a dopant of the first conductivity type into the third semiconductor layer to form a fourth semiconductor layer that touches and lies over the third semiconductor layer, the fourth semiconductor layer having the first conductivity type;
wherein the second semiconductor layer lies completely between the first semiconductor layer and the third semiconductor layer; and
wherein the third semiconductor layer lies completely between the second semiconductor layer and the fourth semiconductor layer.

2. The method of claim 1 , wherein the third semiconductor layer has a dopant concentration that is substantially equal to the dopant concentration of the first semiconductor layer.

3. The method of claim 2 , wherein the fourth semiconductor layer has a dopant concentration that is substantially equal to the dopant concentration of the substrate region.

4. The method of claim 3 and further comprising forming a trench isolation structure that touches and laterally surrounds a portion of the substrate region, the first semiconductor layer, the second semiconductor layer, the third semiconductor layer, and the fourth semiconductor layer.

5. The method of claim 4 and further comprising:
forming a first non-conductive layer that touches and lies over the fourth semiconductor layer; and
forming a metal opening that extends through the first non-conductive layer to expose the fourth semiconductor layer.

6. The method of claim 5 and further comprising:
depositing a metal layer that touches and lies over the first non-conductive layer, and fills up the metal opening; and
etching the metal layer to form a metal contact that touches and lies over the fourth semiconductor layer.

7. The method of claim 6 and further comprising:
forming a second non-conductive layer that touches and lies over the first non-conductive layer and the metal contact; and
forming a contact opening that extends through the second non-conductive layer to expose the metal contact.

8. A method of forming a bidirectional ESD diode structure comprising the following steps:
forming a top diode, the top diode including a first p+ region touching and overlying a first n+ epitaxial layer, the first p+ region forming an anode;
forming a bottom diode, the bottom diode including a second n+ epitaxial layer touching and overlying a p+ substrate region;
forming a p− epitaxial layer between the top diode and the bottom diode, wherein the p− epitaxial layer separates the first n+ epitaxial layer from the second n+ epitaxial layer; and
forming a metal contact in contact with the anode.

9. The method of claim 8 , wherein the first n+ epitaxial layer has a dopant concentration substantially equal to the dopant concentration of the second n+ epitaxial layer.

10. The method of claim 9 , wherein the first p+ region has a dopant concentration substantially equal to the dopant concentration of the p+ substrate region.

11. The method of claim 10 , wherein the p− epitaxial layer lies completely between the second n+ epitaxial layer and the first n+ epitaxial layer.

12. The method of claim 11 , wherein the first n+ epitaxial layer lies completely between the p− epitaxial layer and the first p+ region.

13. The method of claim 12 , further comprising a trench isolation structure that touches and laterally surrounds a portion of the p+ substrate region, the second n+ epitaxial layer, p− epitaxial layer, first n+ epitaxial layer, and the first p+ region.

14. The method of claim 13 , wherein the trench isolation structure includes a polycrystalline silicon core and an isolation structure that lies between the polycrystalline silicon core and the p+ substrate region.

15. A method of forming a bidirectional ESD diode structure comprising the following steps:
epitaxially growing a first n+ epitaxial layer over and touching a p+ substrate to form a bottom diode;
epitaxially growing a p− epitaxial layer over the bottom diode;
epitaxially growing a second n+ epitaxial layer over the p− epitaxial layer;
forming a first p+ region touching and overlying the second n+ epitaxial layer to form a top diode, the first p+ region forming an anode, wherein the p− epitaxial layer separates the first n+ epitaxial layer from the second n+ epitaxial layer; and
forming a metal contact in contact with the anode.

16. The method of claim 15 , wherein the first n+ epitaxial layer has a dopant concentration substantially equal to the dopant concentration of the second n+ epitaxial layer.

17. The method of claim 16 , wherein the first p+ region has a dopant concentration substantially equal to the dopant concentration of the p+ substrate region.

18. The method of claim 17 , wherein the p− epitaxial layer lies completely between the second n+ epitaxial layer and the first n+ epitaxial layer.

19. The method of claim 18 , wherein the second n+ epitaxial layer lies completely between the p− epitaxial layer and the first p+ region.

20. The method of claim 19 , further comprising a trench isolation structure that touches and laterally surrounds a portion of the p+ substrate region, the second n+ epitaxial layer, p− epitaxial layer, first n+ epitaxial layer, and the first p+ region.

Assignees

• Texas Instruments Inc

Inventors

• Tani Toshiyuki
• Yamashita Akihiko
• Kusamaki Motoaki
• Takahashi Kentaro

Classifications

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10W10/014

  using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10D62/115

  Dielectric isolations, e.g. air gaps · CPC title

• H10D8/045

  of PN junction diodes · CPC title

• H10D89/713

  including a PNP transistor and a NPN transistor, wherein each of said transistors has its base region coupled to the collector region of the other transistor, e.g. silicon controlled rectifier [SCR] devices · CPC title