Semiconductor device having buried region and method of fabricating same

Patent metadata

Field	Value
Publication number	US-9761656-B2
Application number	US-201514683710-A
Country	US
Kind code	B2
Filing date	Apr 10, 2015
Priority date	Apr 10, 2015
Publication date	Sep 12, 2017
Grant date	Sep 12, 2017

Abstract

A semiconductor device includes a substrate having a first conductivity type, a high-voltage well having a second conductivity type and formed in the substrate, a drift region formed in the high-voltage well, a drain region formed in the high-voltage well and spaced apart from the drift region, and a buried region having the first conductivity type formed in the high-voltage well between the drift region and the drain region.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a substrate having a first conductivity type;
a high-voltage well having a second conductivity type and formed in the substrate;
a source region formed in the high-voltage well;
a drain region formed in the high-voltage well;
a drift region formed in the high-voltage well between the source region and the drain region, and spaced apart from the source region and the drain region; and
a buried region having the first conductivity type formed in the high-voltage well between the drift region and the drain region,
wherein an upper-side edge of the buried region is deeper than a bottom of the drift region.

2. The semiconductor device of claim 1 , wherein the first conductivity type is P-type and the second conductivity type is N-type, and
the drift region includes:
a P-type top region; and
an N-type grade region formed on top of the P-type top region.

3. The semiconductor device of claim 1 , wherein the first conductivity type is N-type and the second conductivity type is P-type.

4. The semiconductor device of claim 1 , wherein the semiconductor device is a lateral diffused metal oxide semiconductor device, and the drain region has the second conductivity type.

5. The semiconductor device of claim 1 , wherein the semiconductor device is an insulated gate bipolar transistor, and the drain region has the first conductivity type.

6. The semiconductor device of claim 1 , wherein the semiconductor device is a diode.

7. The semiconductor device of claim 1 , further including an insulation layer formed above the drift region,
wherein the buried region is disposed to overlap with an edge portion of the insulation layer, and
the buried region is disposed to overlap or not overlap with the drift region.

8. The semiconductor device of claim 1 , further including:
a source well having the first conductivity type and formed in the high-voltage well on a first side of the drift region opposite to a second side where the drain region is formed;
wherein the source region is formed in the source well.

9. The semiconductor device of claim 8 , further including:
a gate oxide layer disposed above the substrate between the source region and the drain region; and
a gate layer disposed above the gate oxide layer.

10. The semiconductor device of claim 1 , further including:
an interlayer dielectric layer disposed above the substrate; and
a contact layer disposed above the interlayer dielectric layer.

11. A method for fabricating a semiconductor device, the method comprising:
providing a substrate having a first conductivity type;
forming a high-voltage well having a second conductivity type in the substrate;
forming a source region in the high-voltage well;
forming a drain region in the high-voltage well;
forming a drift region in the high-voltage well between the source region and the drain region, and spaced apart from the source region and the drain region; and
forming a buried region having the first conductivity type in the high-voltage well between the drift region and the drain region,
wherein forming the buried region includes forming an upper-side edge of the buried region deeper than a bottom of the drift region.

12. The method of claim 11 , wherein the first conductivity type is P-type and the second conductivity type is N-type.

13. The method of claim 11 , wherein the first conductivity type is N-type and the second conductivity type is P-type.

14. The method of claim 11 , wherein the semiconductor device is a lateral diffused metal oxide semiconductor device, and
forming the drain region includes forming the drain region having the second conductivity type.

15. The method of claim 11 , wherein the semiconductor device is an insulated gate bipolar transistor, and
forming the drain region includes forming the drain region having the first conductivity type.

16. The method of claim 11 , wherein forming the drift region includes:
forming a top region having the first conductivity type in the high-voltage well; and
forming a grade region having the second conductivity to be on top of the top region.

17. The method of claim 11 , further including:
forming a source well having the first conductivity type in the high-voltage well on a first side of the drift region opposite to a second side where the drain region is formed;
wherein forming the source region in the high-voltage well includes forming the source region in the source well.

18. The method of claim 17 , further including:
forming a gate oxide layer above the substrate between the source region and the drain region; and
forming a gate layer above the gate oxide layer.

19. The method of claim 11 , further including:
forming an interlayer dielectric layer above the substrate; and
forming a contact layer above the interlayer dielectric layer.

20. The method of claim 11 , wherein forming the buried region includes implanting a dopant having the first conductivity type into a defined region in the high-voltage well.

Assignees

• Macronix Int Co Ltd

Inventors

• Chien Yu-Chin
• Chan Ching-Lin

Classifications

• H01L29/8618

  Electricity · mapped topic

• H01L29/66689

  Electricity · mapped topic

• H01L29/0634

  Electricity · mapped topic

• H01L29/1087

  Electricity · mapped topic

• H01L29/7816

  Electricity · mapped topic