Semiconductor device having first and second layers with opposite conductivity types

US9786796B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9786796-B2
Application numberUS-201514688640-A
CountryUS
Kind codeB2
Filing dateApr 16, 2015
Priority dateJun 4, 2009
Publication dateOct 10, 2017
Grant dateOct 10, 2017

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A semiconductor device having first through third layers. The first layer has a conductivity type that is different from a conductivity type of the second layer. A peak value of an impurity concentration of a portion of the third layer is greater than a peak value of an impurity concentration of the second layer. The semiconductor device allows a decrease in the forward voltage drop and also allows an improvement of the safe operating area tolerance. Thus, it is possible to decrease the forward voltage drop, improve the maximum reverse voltage, and suppress oscillations at the time of recovery.

First claim

Opening claim text (preview).

What is claimed is: 1. A semiconductor device comprising: a first electrode; a first layer located on said first electrode and having a first conductivity type; a second layer located on said first layer and having a second conductivity type different from said first conductivity type; a third layer located on said second layer and having a first portion, said first portion having said second conductivity type and having a peak value of an impurity concentration higher than the peak value of the impurity concentration in said second layer; a second electrode located on said third layer; a trench structure located in said first portion and said second layer a dielectric film; a third electrode disposed within said trench structure; and a diffusion layer located between said third layer and said second electrode and having said first conductivity type having a peak value of an impurity concentration higher than the peak value of the impurity concentration in said first layer, wherein said trench structure is completely surrounded by said second conductivity type in an area extending from said second layer to said third layer, said dielectric film is disposed between said third electrode and said second electrode, a first insulation film is disposed between said dielectric film and said third electrode, a second insulation layer is disposed between said dielectric film and said second electrode, and the second insulation layer is disposed between said third electrode and said second electrode. 2. The semiconductor device according to claim 1 , wherein said trench structure extends through said first portion. 3. The semiconductor device according to claim 1 , further comprising, between said second layer and said third layer, a fourth layer having said second conductivity type, having a peak value of an impurity concentration higher than the peak value of the impurity concentration in said second layer, and having a peak value of an impurity concentration lower than the peak value of the impurity concentration in said first portion. 4. The semiconductor device according to claim 3 , wherein said trench structure extends through said first portion and said fourth layer. 5. The semiconductor device according to claim 1 , further comprising a barrier metal layer disposed between said dielectric film and said second electrode. 6. The semiconductor device according to claim 5 , wherein said second insulation layer is disposed between said dielectric film and said barrier metal layer. 7. The semiconductor device according to claim 1 , further comprising a barrier metal layer disposed between said dielectric film and said second electrode, wherein said barrier metal layer is located between said diffusion layer and said second electrode. 8. The semiconductor device according to claim 7 , wherein said diffusion layer is formed such that the barrier layer does not come into contact with said third layer.

Assignees

Inventors

Classifications

  • H10D8/00Primary

    Diodes (variable-capacitance diodes H10D1/64; gated diodes H10D12/00) · CPC title

  • Electricity · mapped topic

  • Electricity · mapped topic

  • H01L29/861Primary

    Electricity · mapped topic

  • Electricity · mapped topic

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What does patent US9786796B2 cover?
A semiconductor device having first through third layers. The first layer has a conductivity type that is different from a conductivity type of the second layer. A peak value of an impurity concentration of a portion of the third layer is greater than a peak value of an impurity concentration of the second layer. The semiconductor device allows a decrease in the forward voltage drop and also al…
Who is the assignee on this patent?
Mitsubishi Electric Corp
What technology area does this patent fall under?
Primary CPC classification H10D8/00. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Oct 10 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).