Conductive structures for microfeature devices and methods for fabricating microfeature devices

Patent metadata

Field	Value
Publication number	US-9313902-B2
Application number	US-201213538891-A
Country	US
Kind code	B2
Filing date	Jun 29, 2012
Priority date	Aug 19, 2004
Publication date	Apr 12, 2016
Grant date	Apr 12, 2016

Abstract

Methods for fabricating conductive structures on and/or in interposing devices and microfeature devices that are formed using such methods are disclosed herein. In one embodiment, a method for fabricating interposer devices having substrates includes forming a plurality of conductive sections on a first substrate in a first pattern. The method continues by forming a plurality of conductive sections on a second substrate in a second pattern. The method further includes constructing a plurality of conductive lines in a common third pattern on both the first substrate and the second substrate. The conductive lines can be formed on the first and second substrates either before or after forming the first pattern of conductive sections on the first substrate and/or forming the second pattern of conductive sections on the second substrate.

First claim

I claim:

1. A method for fabricating interposer devices having substrates, the method comprising:
forming a plurality of conductive sections on a first side of a first interposer substrate in a first pattern;
forming a plurality of conductive sections on a first side of a second interposer substrate in a second pattern different than the first pattern, wherein the second interposer substrate is separate and discrete from the first interposer substrate; and
constructing a plurality of conductive lines on both the first interposer substrate and the second interposer substrate, wherein the first interposer substrate and the second interposer substrate have the same predetermined arrangement of conductive lines,
wherein the plurality of conductive lines are formed either before or after forming the conductive sections in the first pattern and/or forming the conductive sections in the second pattern on the first and second interposer substrates, respectively,
wherein the conductive lines at the first side of the first interposer substrate are positioned to be directly electrically coupled to corresponding connectors on a first microelectronic die to which the first interposer substrate will be attached, and
wherein the conductive lines at the first side of the second interposer substrate are positioned to be directly electrically coupled to corresponding connectors on a second microelectronic die to which the second interposer substrate will be attached, wherein the first interposer substrate remains separate and discrete from the second interposer substrate before and after constructing the plurality of conductive lines.

2. The method of claim 1 wherein forming a plurality of conductive sections on a first interposer substrate in a first pattern comprises using a single photolithographic and etching process.

3. The method of claim 1 wherein forming a plurality of conductive sections on a second interposer substrate in a second pattern comprises using a single photolithographic and etching process.

4. The method of claim 1 wherein:
forming a plurality of conductive sections on a first interposer substrate in a first pattern comprises using a single photolithographic and etching process; and
forming a plurality of conductive sections on a second interposer substrate in a second pattern comprises using a single photolithographic and etching process.

5. The method of claim 1 wherein forming a plurality of conductive sections on a first interposer substrate in a first pattern comprises:
depositing a seed layer onto the first side of the first interposer substrate and a second side of the first interposer substrate opposite the first side;
forming a first pattern in a resist layer on the seed layer, the first pattern having an arrangement of apertures corresponding to a desired arrangement of openings in the resist layer;
forming openings in the resist layer,
depositing a conductive material into the openings to construct conductive sections on and/or in the first interposer substrate in the first pattern, wherein the individual conductive sections include a first section at the first side of the first interposer substrate and a second section at the second side of the first interposer substrate; and
removing selected portions of the resist layer.

6. The method of claim 1 wherein forming a plurality of conductive sections on a second interposer substrate in a second pattern comprises:
depositing a conductive material onto the first side of the second interposer substrate and a second side of the second interposer substrate opposite the first side; and
removing selected portions of the conductive material after selectively forming passages through the conductive material and the second interposer substrate to form a plurality of conductive sections on and/or in the second interposer substrate in a second pattern, the individual conductive sections including a first section at the first side of the second interposer substrate and a second section at the second side of the second interposer substrate.

7. The method of claim 1 wherein forming a plurality of conductive sections on a first interposer substrate in a first pattern comprises:
depositing a conductive material onto the first side of the first interposer substrate and a second side of the first interposer substrate opposite the first side; and
removing selected portions of the conductive material after selectively forming passages through the conductive material and the first interposer substrate to form a plurality of conductive sections on and/or in the first interposer substrate in a first pattern, the individual conductive sections including a first section at the first side of the first interposer substrate and a second section at the second side of the first interposer substrate.

8. The method of claim 1 wherein forming a plurality of conductive sections on a second interposer substrate in a second pattern comprises:
depositing a seed layer onto the first side of the second interposer substrate and a second side of the second interposer substrate opposite the first side;
forming a second pattern in a resist layer on the seed layer, the second pattern having an arrangement of apertures corresponding to a desired arrangement of openings in the resist layer;
forming openings in the resist layer,
depositing a conductive material into the openings to construct conductive sections on and/or in the second interposer substrate in the second pattern, wherein the individual conductive sections include a first section at the first side of the second interposer substrate and a second section at the second side of the second interposer substrate; and
removing selected portions of the resist layer.

9. The method of claim 1 wherein constructing conductive lines comprises:
selectively forming passages through the first interposer substrate and/or the second interposer substrate in a predetermined third pattern corresponding to a desired arrangement of conductive lines; and
depositing a conductive fill material into the individual passages to form interconnects extending through the first interposer substrate and/or the second interposer substrate.

10. The method of claim 9 wherein selectively forming passages through the first interposer substrate and/or the second interposer substrate comprises using a Computer Numerically Controlled (CNC) drilling process to form the passages.

11. The method of claim 9 wherein selectively forming passages through the first interposer substrate and/or the second interposer substrate comprises using a laser to form the passages.

12. The method of claim 9 wherein selectively forming passages through the first interposer substrate and/or the second interposer substrate comprises using a stamping process to form the passages.

13. The method of claim 1 wherein forming a plurality of conductive sections on a first interposer substrate in a first pattern comprises forming a plurality of first conductive sections at the first side of the first interposer substrate and a plurality of corresponding second conductive sections at a second side of the first interposer substrate.

14. The method of claim 1 wherein forming a plurality of conductive sections on a second interposer substrate in a second pattern comprises forming a plurality of first conductive sections at the first side of the second interposer substrate and a plurality of corresponding second conductive sections at a second side of the second interposer substrate.

15. The method of claim 1 , wherein the connectors on the first microelectronic die or the second

Assignees

• Johnson Mark S
• Micron Technology Inc

Inventors

• Johnson Mark S

Classifications

• H05K1/0287

  having an universal lay-out, e.g. pad or land grid patterns or mesh patterns · CPC title

• H05K3/108

  by semi-additive methods; masks therefor (characterised by metallic etch mask H05K3/062; electroplating methods or apparatus H05K3/241) · CPC title

• H05K3/428 Primary

  initial plating of through-holes in substrates having a metal pattern · CPC title

• H05K2201/10378

  Interposers · CPC title

• H05K2201/09609

  Via grid, i.e. two-dimensional array of vias or holes in a single plane · CPC title