Wiring substrate

Patent metadata

Field	Value
Publication number	US-9826639-B2
Application number	US-201615351814-A
Country	US
Kind code	B2
Filing date	Nov 15, 2016
Priority date	Dec 8, 2015
Publication date	Nov 21, 2017
Grant date	Nov 21, 2017

Abstract

A wiring substrate includes an insulating layer, a first wiring layer and a second wiring layer on opposite sides of the insulating layer, and a via piercing through the first wiring layer and the insulating layer to electrically connect to the second wiring layer. The via includes an end portion projecting from a first surface of the first wiring layer facing away from the insulating layer. A surface of the end portion facing in the same direction as the first surface of the first wiring layer is depressed to be deeper in the center than in the periphery.

First claim

What is claimed is:

1. A wiring substrate, comprising:
an insulating layer;
a first wiring layer and a second wiring layer on opposite sides of the insulating layer; and
a via piercing through the first wiring layer and the insulating layer to electrically connect to the second wiring layer, the via including an end portion projecting from a first surface of the first wiring layer facing away from the insulating layer,
wherein a surface of the end portion facing in a same direction as the first surface of the first wiring layer is depressed to be deeper in a center than in a periphery thereof.

2. The wiring substrate as claimed in claim 1 , wherein
the via fills in a through hole piercing through the first wiring layer and the insulating layer, and
the end portion extends onto the first surface of the first wiring layer around the through hole.

3. The wiring substrate as claimed in claim 1 , further comprising:
a solder resist layer provided on the first surface of the first wiring layer, and including a plurality of openings that expose the first wiring layer and the end portion,
wherein the first wiring layer and the end portion exposed in the plurality of openings define external connection pads.

4. The wiring substrate as claimed in claim 1 , further comprising:
a solder resist layer provided on the first surface of the first wiring layer, and including an opening that exposes the first wiring layer, the solder resist layer covering the surface of the end portion,
wherein the first wiring layer exposed in the opening defines an external connection pad.

5. The wiring substrate as claimed in claim 1 , wherein an edge of a part of the first wiring layer that contacts a sidewall of the via at a second surface of the first wiring layer opposite to the first surface projects toward the insulating layer relative to the second surface.

6. The wiring substrate as claimed in claim 1 , wherein an edge of a part of the first wiring layer that contacts a sidewall of the via at the first surface of the first wiring layer is rounded.

7. The wiring substrate as claimed in claim 1 , wherein
the second wiring layer includes an external connection pad, and
the via includes another end portion directly joined to the external connection pad.

8. The wiring substrate as claimed in claim 1 , wherein
a plurality of mounting regions each for mounting an electronic component are arranged in a grid on the insulating layer, and
each of the plurality of mounting regions includes the first wiring layer, a plurality of pads for mounting the electronic component included in the second wiring layer, and the via.

Assignees

• Shinko Electric Ind Co

Inventors

• Denda Tatsuaki
• Hoshino Osamu

Classifications

• H05K2203/0733

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• H05K2201/10234

  Metallic balls · CPC title

• H05K2201/09745

  Recess in conductor, e.g. in pad or in metallic substrate · CPC title

• H05K2201/09563

  Metal filled via · CPC title

• H05K3/428

  initial plating of through-holes in substrates having a metal pattern · CPC title