Circuit board formation using organic substrates

Patent metadata

Field	Value
Publication number	US-9760002-B2
Application number	US-201514950673-A
Country	US
Kind code	B2
Filing date	Nov 24, 2015
Priority date	Aug 19, 2014
Publication date	Sep 12, 2017
Grant date	Sep 12, 2017

Abstract

A method of forming a circuit board includes forming a conductive pattern on a substrate; forming a first negative resist on the substrate after formation of the conductive pattern; partially exposing the first negative resist on the surface of the conductive pattern to form a first via exposure portion; forming a second negative resist on the substrate after formation of the first via exposure portion; partially exposing the second negative resist on the first via exposure portion to form a second via exposure portion larger than the first via exposure portion; developing the first negative resist and the second negative resist after formation of the second via exposure portion to form a via opening reaching the conductive pattern; and filling the via opening with a conductive material.

First claim

The invention claimed is:

1. A method of forming a circuit board, the method comprising:
forming a conductive pattern on a substrate;
forming a first negative resist on the substrate after formation of the conductive pattern;
partially exposing the first negative resist on the surface of the conductive pattern to form a first via exposure portion;
forming a second negative resist on the substrate after formation of the first via exposure portion;
partially exposing the second negative resist on the first via exposure portion to form a second via exposure portion larger than the first via exposure portion using a photomask, wherein the first via exposure portion comprises a first sub-portion that overlaps a masked portion of the photomask and the second via exposure portion and a second sub-portion that overlaps an un-masked portion of the photomask and does not overlap the second via exposure portion;
wherein partially exposing the second negative resist causes the second via exposure portion to be unexposed, the first sub-portion of the first via exposure portion to be unexposed, and the second sub-portion of the first via exposure portion to be exposed;

developing the first negative resist and the second negative resist after formation of the second via exposure portion to form a via opening reaching the conductive pattern; and
filling the via opening with a conductive material.

2. The method of claim 1 , wherein;
forming the second via exposure portion includes simultaneously partially exposing the second negative resist outside of the first via exposure portion to form a conductive wiring exposure portion;
forming a via opening reaching the conductive pattern includes simultaneously forming a wiring opening in the second negative resist; and
filling the opening with a conductive material includes simultaneously filling the wiring opening with the conductive material.

3. The method of claim 2 , wherein filling the opening with a conductive material includes:
forming a seed layer on the surface of the substrate excluding the via opening and the wiring opening, and in the interior of the via opening and the interior of the wiring opening;
forming a conductive layer on the seed layer using electroplating; and
polishing the surface of the substrate to leave the conductive material only in the via opening and the wiring opening.

4. The method of claim 1 , wherein filling the opening with a conductive material includes:
forming a seed layer on the surface of the substrate excluding the via opening and in the interior of the via opening;
forming a conductive layer on the seed layer using electroplating; and
polishing the surface of the substrate to leave the conductive material only in the via opening.

5. The method of claim 1 , wherein the first negative resist and the second negative resist are used as interlayer insulating layers in the circuit board.

6. The method of claim 1 , wherein forming the first via exposure portion includes direct exposure of the first negative resist using a laser.

7. The method of claim 1 , wherein the substrate is an organic substrate, and the circuit board comprises an interposer.

Assignees

• IBM

Inventors

• Mori Hiroyuki
• Noma Hirokazu
• Okamoto Keishi

Classifications

• H05K3/4679

  Aligning added circuit layers or via connections relative to previous circuit layers · CPC title

• H05K2203/1453

  Applying the circuit pattern before another process, e.g. before filling of vias with conductive paste, before making printed resistors · CPC title

• H05K2203/0577

  Double layer of resist having the same pattern · CPC title

• G03F7/0035 Primary

  Multiple processes, e.g. applying a further resist layer on an already in a previously step, processed pattern or textured surface · CPC title

• H05K2201/09509

  Blind vias, i.e. vias having one side closed · CPC title