Wiring substrate

Patent metadata

Field	Value
Publication number	US-9997448-B1
Application number	US-201715805660-A
Country	US
Kind code	B1
Filing date	Nov 7, 2017
Priority date	Dec 9, 2016
Publication date	Jun 12, 2018
Grant date	Jun 12, 2018

Abstract

A wiring substrate includes a flexible insulation substrate, a first wiring layer formed on an upper surface of the insulation substrate, a second wiring layer formed on a lower surface of the insulation substrate, and through wiring bonded to the first wiring layer and the second wiring layer and formed in a through hole extending through the first wiring layer, the insulation substrate, and the second wiring layer. The through wiring includes a projection that extends along a lower surface of the second wiring layer located outside the through hole. An upper surface of the through wiring is flush with an upper surface of the first wiring layer.

First claim

The invention claimed is:

1. A wiring substrate comprising:
a flexible insulation substrate;
a first wiring layer formed on an upper surface of the insulation substrate;
a second wiring layer formed on a lower surface of the insulation substrate; and
a through wiring formed in a through hole extending through the first wiring layer, the insulation substrate, and the second wiring layer, the through wiring being bonded to the first wiring layer and the second wiring layer and, wherein
the through wiring includes a projection that extends along a lower surface of the second wiring layer located outside the through hole, and
an upper surface of the through wiring is flush with an upper surface of the first wiring layer.

2. The wiring substrate according to claim 1 , wherein:
the projection extends in an annular manner on the lower surface of the second wiring layer located outside the through hole; and
the projection includes an upper surface that is directly bonded to the lower surface of the second wiring layer.

3. The wiring substrate according to claim 1 , wherein:
the through wiring includes a barrel that fills the through hole;
the projection is integrally formed with the barrel and projects downward from the lower surface of the second wiring layer; and
the barrel includes:
an upper end portion including a circumferential surface directly bonded to an inner surface portion of the first wiring layer;
a lower end portion including a circumferential surface directly bonded to an inner surface portion of the second wiring layer; and
a middle portion located between the upper end portion and the lower end portion and including a circumferential surface, wherein the circumferential surface of the middle portion is in contact with an inner surface portion of the insulation substrate.

4. The wiring substrate according to claim 1 , wherein the through wiring is formed from a plating metal.

5. The wiring substrate according to claim 1 , further comprising:
a first protective layer that covers a portion of the first wiring layer and includes an opening exposing the upper surface of the through wiring and the upper surface of the first wiring layer located at an outer side of the through wiring; and
a second protective layer that covers a portion of the second wiring layer and the through wiring and includes an opening exposing a portion of the lower surface of the second wiring layer.

6. The wiring substrate according to claim 5 , further comprising:
a first surface-processed layer that covers a surface of the first wiring layer and the upper surface of the through wiring that are exposed from the first protective layer; and
a second surface-processed layer that covers a surface of the second wiring layer exposed from the second protective layer.

7. A semiconductor device comprising:
a wiring substrate according to claim 1 ; and
at least one electronic component mounted on the wiring substrate.

Assignees

• Shinko Electric Ind Co
• Shinko Electric Ind Co

Inventors

• Sato Kiyokazu
• Imai Mitsuyoshi
• Hoshino Osamu

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W72/20

  Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps · CPC title

• H10W70/685

  comprising multiple insulating layers · CPC title

• H10W70/635

  Through-vias · CPC title

• H10W70/688

  Flexible insulating substrates · CPC title