Method of manufacturing package substrate and semiconductor package

Patent metadata

Field	Value
Publication number	US-9905438-B2
Application number	US-201715466063-A
Country	US
Kind code	B2
Filing date	Mar 22, 2017
Priority date	Nov 27, 2014
Publication date	Feb 27, 2018
Grant date	Feb 27, 2018

Abstract

A package substrate and a semiconductor package are provided. The package substrate includes an insulating layer having opposing first and second surfaces; a first wiring layer formed in the insulating layer, exposed from the first surface of the insulating layer, and having a plurality of first conductive pads; a second wiring layer formed in the insulating layer, exposed from the second surface, and having a plurality of second conductive pads; a third wiring layer formed on the first surface and electrically connected with the first wiring layer; a plurality of first metal bumps formed on the first conductive pads corresponding; and at least one conductive via vertically embedded in the insulating layer and electrically connected to the second and third wiring layers. Therefore, the surfaces of first conductive pads are reduced, and the non-wetting between the first conductive pads and the solder materials formed on conductive bumps is avoided.

First claim

What is claimed is:

1. A method of manufacturing a package substrate, comprising:
preparing a first carrier and a second carrier, the first carrier having a first wiring layer having a plurality of first conductive pads, and the second carrier having a second wiring layer facing the first wiring layer on the first carrier and the second carrier and having a plurality of second conductive pads;
forming an insulating layer that encapsulates the first wiring layer and the second wiring layer and has opposing first and second surfaces;
removing the first carrier and the second carrier such that the first wiring layer is exposed from the first surface, and the second wiring layer is exposed from the second surface;
forming in the insulating layer at least one conductive via that is electrically connected with the second wiring layer; and
forming on the first surface a third wiring layer that is electrically connected with the at least one conductive via, and forming first metal bumps on the first conductive pads correspondingly, wherein each of the first metal bumps has an area projected onto the first surface that is less than an area of a corresponding one of the first conductive pads.

2. The method of claim 1 , wherein the first carrier and the second carrier are prepared by:
providing a board having the first carrier and the second carrier stacked on the first carrier;
forming the first wiring layer having the first conductive pads on the first carrier, and forming the second wiring layer having the second conductive pads on the second carrier; and
separating the first carrier and the second carrier.

3. The method of claim 1 , wherein the first carrier and the second carrier have conductive layers formed on surfaces thereof, the first wiring layer and the second wiring layer are formed on the conductive layers, and after the first carrier and the second carrier are removed, the first wiring layer has a surface that is lower than the first surface, and the second wiring layer has a surface that is lower than the second surface.

4. The method of claim 1 , wherein the insulating layer is formed by forming an insulating material on at least one of the first carrier and the second carrier, and pressing the first carrier and second carrier.

5. The method of claim 1 , wherein the insulating layer is formed by providing an insulating material, and pressing the first wiring layer and the second wiring layer into the insulating material when the first wiring layer faces the second wiring layer, so as to form the insulating layer.

6. The method of claim 1 , wherein the insulating layer is formed by filling an insulating material between the first wiring layer and the second wiring layer when the first wiring layer faces the second wiring layer.

7. The method of claim 1 , further comprising forming a plurality of second metal bumps on the second conductive pads correspondingly when the first metal bumps are formed.

8. The method of claim 7 , wherein each of the second metal bumps has an area projected onto the second surface that is less than an area of a corresponding one of the second conductive pads.

9. A method of manufacturing a semiconductor package, comprising:
disposing at least one semiconductor component on the package substrate of claim 1 ; and
forming on the package substrate an encapsulant that encapsulates the semiconductor component.

10. The method of claim 9 , wherein the semiconductor component is mounted on the first surface of the package substrate in a flip-chip manner.

11. The method of claim 10 , wherein the semiconductor component has a solder material that encapsulates the first metal bumps.

12. The method of claim 9 , wherein the semiconductor component is mounted on the second surface of the package substrate in a flip-chip manner.

13. The method of claim 12 , wherein the package substrate further comprises a plurality of second metal bumps formed on each of the second conductive pads correspondingly, and the semiconductor component has a soldering material that encapsulates the second metal bumps.

Assignees

• Siliconware Precision Industries Co Ltd

Inventors

• Sun Ming Chen
• Lin Chun Hsien
• Shen Tzu Chieh
• Chiu Shih Chao
• Pai Yu Cheng

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W74/114

  by a substrate and the encapsulations · CPC title

• H10W72/07236

  Soldering or alloying · CPC title

• H10W72/252

  comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu · CPC title

• H10W72/241

  Dispositions, e.g. layouts · CPC title