Tester and method for testing a strip of devices

Patent metadata

Field	Value
Publication number	US-9285422-B2
Application number	US-201213465651-A
Country	US
Kind code	B2
Filing date	May 7, 2012
Priority date	May 7, 2012
Publication date	Mar 15, 2016
Grant date	Mar 15, 2016

Abstract

A tester configured to test a strip of devices is provided. The tester may include a communications system, a plurality of communication lines, a plurality of multiplexors, each multiplexor having at least two outputs, wherein each multiplexor is configured to receive a signal generated by the communications system via one of the plurality of communication lines, and each multiplexor may be selectably coupled to at least two of the devices in the strip of devices. The tester may be configured to index the plurality of communication lines to a first subset of the devices, initiate at least one test, command the devices to generate data for each of the at least one tests, retrieve data from a first set of the devices, and retrieve data from a second set of the devices.

First claim

What is claimed is:

1. A device, comprising:
a memory;
a test circuit operably coupled to the memory and configure to provide data to be stored in the memory during a test of the device;
a first external input interface to the device, the first external input interface electrically coupled to the test circuit and configured to provide a command to the test circuit upon receipt of a signal, the first external input interface located on a first side of the device;
a first external output interface from the device located on a second side of the device; and
a signal line trace electrically connected between the first external input interface and the first external output interface.

2. The device of claim 1 , further comprising:
an external ground input interface to the device;
an external ground output interface from the device; and
a ground trace electrically connected between the external ground input interface and the external ground output interface, the ground line trace having a first end located generally at one side of the device and having a second end located generally at the second side of the device.

3. The device of claim 1 , further comprising:
an external power input interface to the device;
an external power output interface from the device; and
a power trace connected between the external power input interface and the external power output interface, the power line trace having a first end located generally at one side of the device and having a second end located generally at the second side of the device.

4. The device of claim 1 , further comprising:
a processor coupled to the memory, wherein the processor is configured to calibrate the device based upon the data stored in the memory.

5. The device of claim 1 , wherein the first external input interface is an interrupt input interface.

6. The device of claim 5 , wherein the test circuitry is configured to generate test data when the interrupt input interface receives the signal and to store the generated test data in the memory.

7. The device of claim 1 , wherein the device is a microelectricalmechanical device.

8. The device of claim 7 , wherein the device is a sensor.

9. The device of claim 8 , wherein the device is an accelerometer.

10. The device of claim 8 , wherein the device is a gyroscope.

11. The device of claim 7 , wherein the device is an actuator.

12. A method of testing a plurality of devices, comprising:
indexing a plurality of communication lines from a tester to a first set of the plurality of devices, wherein each communication line from the tester is selectively coupled to at least two devices of the first set of devices via one of a plurality of multiplexors, each of the plurality of devices comprising a first external input interface, the first external input interface electrically coupled to a test circuit and configured to provide a command to the test circuit upon receipt of a signal, the first external input interface located on a first side of each of the plurality of devices, a first external output interface located on a second side of each of the plurality of devices, and a signal line trace electrically connected between the first external input interface and the first external output interface;
initiating at least one test; and
simultaneously commanding at least the at least two devices coupled to the tester via the plurality of communications lines to generate data for each of the at least one test.

13. The method of claim 12 , further comprising:
retrieving data from a first subset of the first set of devices coupled to the tester via one of the plurality of multiplexors.

14. The method of claim 13 , further comprising:
analyzing the retrieved data to generate calibration data for each of the first set of plurality of devices; and
programming the first set of plurality of devices with the generated calibration data.

15. The method of claim 14 , further comprising:
selectively controlling the plurality of multiplexors to index to a next subset of the set of devices coupled to the tester via one of the plurality of multiplexors; and
retrieving data from the next subset of the devices coupled to the tester via one of the plurality of multiplexors.

16. The method of claim 15 , further comprising:
indexing the plurality of communication lines from the tester to a second set of the plurality of devices, wherein each communication line from the tester is selectively coupled to at least two devices of the second set of devices via one of a plurality of multiplexors.

17. The method of claim 12 , further comprising:
calibrating, by a processor in each device, the devices based upon the generated data.

18. The method of claim 12 , wherein the plurality of devices are arranged in a plurality of rows and each multiplexor is configured to be coupled to devices in at least two rows, the method further comprising:
applying, by the tester, power to each of the plurality of devices via a plurality of power traces coupling a power input for each device in each row of devices; and
applying, by the tester, ground to each of the plurality of devices via a plurality of ground traces coupling a ground input for each device in each row of devices.

19. The method of claim 18 , wherein a trace couples an interrupt input of each the devices in each row, and the commanding further comprises commanding each of the plurality of devices to generate data for each of the at least one tests.

20. The method of claim 12 , further comprising storing, in a memory in each device, the data generated for each device.

Assignees

• Dawson Chad S
• Hooper Stephen R
• Jones Peter T
• Schlarmann Mark E
• Freescale Semiconductor Inc

Inventors

• Dawson Chad S
• Hooper Stephen R
• Jones Peter T
• Schlarmann Mark E

Classifications

• B81C99/005

  Test apparatus · CPC title

• B81C99/0045

  End test of the packaged device · CPC title

• B81B2207/03

  Electronic circuits for micromechanical devices which are not application specific, e.g. for controlling, power supplying, testing, protecting · CPC title

• G01R31/2844

  using test interfaces, e.g. adapters, test boxes, switches, PIN drivers (G01R31/2889 takes precedence) · CPC title

• G01R31/2829

  Testing of circuits in sensor or actuator systems (testing of apparatus for measuring electric or magnetic variables G01R35/00; testing of indicating or recording apparatus G01D; in airbag systems B60R21/0173; checking gas analysers G01N33/007; monitoring or fail-safe circuits for electromagnets H01F7/1844) · CPC title