In situ on the fly on-chip variation measurement

Patent metadata

Field	Value
Publication number	US-9448281-B2
Application number	US-201314134259-A
Country	US
Kind code	B2
Filing date	Dec 19, 2013
Priority date	Dec 19, 2013
Publication date	Sep 20, 2016
Grant date	Sep 20, 2016

Abstract

A methodology and circuits for integrated circuit design are provided. A first electronic design file for an integrated circuit is provided. The first electronic design file for the integrated circuit has a timing measurement circuit thereon. Based on the first electronic design file, a number of integrated circuits are manufactured. These manufactured integrated circuits have respective timing measurement circuits arranged at predetermined locations thereon. The timing measurement circuits are used to measure a number of respective timing delay values, which are subject to manufacturing variation, on the integrated circuits. The measured timing delay values are used to set how an auto-place and route tool arranges blocks in a second electronic design file, which is routed after the timing delay values are measured, to account for any measured manufacturing variation.

First claim

What is claimed is:

1. An integrated circuit (IC), comprising:
a clock tree including a plurality of signal paths which stem from a clock source and each of which includes one or more delay elements that are subject to manufacturing variation, wherein the clock source is configured to operate independent of the one or more delay elements; and
a timing measurement circuit which is distinct from the one or more delay elements and which has first and second inputs coupled to respective first and second predetermined locations on one or more of the signal paths, wherein the timing measurement circuit is configured to provide a timing delay value which is indicative of a timing delay as measured between the first and second predetermined locations.

2. The IC of claim 1 , further comprising:
a test probe output interface by which the timing measurement circuit is configured to provide the timing delay value to an external test probe device.

3. The IC of claim 1 , wherein the timing measurement circuit is a time to digital converter.

4. The IC of claim 3 , wherein the time to digital converter provides a multi-bit digital value corresponding to a first timing delay value as measured between the first and second inputs, wherein the multi-bit digital value can vary between a first digital value corresponding to a predetermined maximum timing delay value and a second, different digital value corresponding to a predetermined minimum timing delay value.

5. The IC of claim 1 , wherein the timing measurement circuit is a time to current converter.

6. The IC of claim 5 , wherein the time to current converter provides a current level value corresponding to a first timing delay value as measured between the first and second inputs, wherein the current level value can vary between a first current level value corresponding to a predetermined maximum timing delay value and a second current level value corresponding to a predetermined minimum timing delay value, and wherein the first current level value is different from the second current level value.

7. The IC of claim 6 , wherein the time to current converter comprises:
first and second input terminals between which first and second signals whose edges exhibit the first timing delay value are to be applied;
a clock input terminal on which a clock signal is to be received;
first logic circuitry to provide a first output current signal whose width represents an overlap between the clock signal and the first signal; and
second logic circuitry to provide a second output current signal whose width represents an overlap between the clock signal and the second signal; and wherein the IC further comprises:
analysis circuitry to determine the first timing delay value between the edges of the first and second signals by comparing the first and second output current signals.

8. The IC of claim 7 , wherein the time to current converter further comprises:
a test signal terminal on which a test signal is to be provided;
wherein when the test signal is in a first state the first output current signal is present at an output terminal of the time to current converter and the second output current signal is blocked from the output terminal; and
wherein when the test signal is in a second state the second output current signal is present at the output terminal of the time to current converter and the first output current signal is blocked from the output terminal.

9. The IC according to claim 7 , wherein the first and second logic circuitry provide the first and second output current signals concurrently, and wherein the clock signal is independent of the first and second signals.

10. The IC of claim 1 , further comprising:
a control circuit configured to enable the timing measurement circuit during a test mode when the clock source is enabled and further configured to disable the timing measurement circuit in a low-power mode.

11. A methodology for integrated circuit design, comprising:
providing a first electronic design file for an integrated circuit comprising a timing measurement circuit and a signal path made up of delay elements, wherein the timing measurement circuit has first and second inputs coupled to first and second predetermined locations, respectively, on the signal path, and wherein the timing measurement circuit is distinct from the delay elements of the signal path;
based on the first electronic design file, manufacturing a plurality of integrated circuits having respective timing measurement circuits arranged at predetermined locations on the respective integrated circuits;
using the plurality of timing measurement circuits to measure a plurality of timing delay values, respectively, on the plurality of manufactured integrated circuits, respectively; and
using the measured timing delay values to set how an auto-place and route tool arranges blocks in a second electronic design file, which is routed after the plurality of timing delays are measured, to account for measured manufacturing variation.

12. The methodology of claim 11 , wherein a timing delay value is measured between first and second signals on an integrated circuit, and wherein measuring the timing delay value comprises:
identifying a timing delay between a first edge of the first signal and a second edge of the second signal; and
providing a multi-bit digital value corresponding to the timing delay value.

13. The methodology of claim 12 , wherein the first edge and the second edge are both rising edges or are both falling edges.

14. The methodology of claim 12 , wherein the multi-bit digital value can vary between a first digital value corresponding to a predetermined maximum timing delay value and a second, different digital value corresponding to a predetermined minimum timing delay value.

15. The methodology of claim 11 , wherein a timing delay value is measured between first and second signals on an integrated circuit, and wherein measuring the timing delay value comprises:
identifying a timing delay between a first edge of the first signal and a second edge of the second signal; and
providing a current signal having a current level which corresponds to the timing delay value.

16. The methodology of claim 11 , further comprising:
providing the first electronic design file further comprising a second timing measurement circuit and a second signal path made up of second delay elements, wherein the second timing measurement circuit has third and fourth inputs coupled to third and fourth predetermined locations, respectively, on the second signal path, and wherein the signal path and the second signal path originate from a common clock source.

17. A time to current converter, comprising:
first and second input terminals between which first and second signals whose edges exhibit a timing delay value are to be applied;
a clock input terminal on which a clock signal is to be received;
first logic circuitry to provide a first output current signal whose width represents an overlap between the clock signal and the first signal;
second logic circuitry to provide a second output current signal whose width represents an overlap between the clock signal and the second signal; and
analysis circuitry to compare the first and second output current signals to determine the timing delay value between the edges of the first and second signals.

18. The time to current converter of claim 17 , further comprising:
a test signal terminal on which a test signal is to be provided;
wherein when the test signal is in a first state the first output cu

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chien Jinn-Yeh
• Peng Yung-Chow
• Yang Chung-Chieh
• Lin Kuan-Yu

Classifications

• G01R31/31725

  Timing aspects, e.g. clock distribution, skew, propagation delay (for tester hardware G01R31/31937) · CPC title

• G01R31/31718

  Logistic aspects, e.g. binning, selection, sorting of devices under test, tester/handler interaction networks, Test management software, e.g. software for test statistics or test evaluation, yield analysis (mechanical aspects G01R31/2808, G01R31/2851) · CPC title

• G01R31/31727 Primary

  Clock circuits aspects, e.g. test clock circuit details, timing aspects for signal generation, circuits for testing clocks (G01R31/31725 takes precedence; concerning scan test G01R31/318552, for tester hardware G01R31/31922) · CPC title