Efficient method of retesting integrated circuits

Patent metadata

Field	Value
Publication number	US-2016320444-A1
Application number	US-201615192418-A
Country	US
Kind code	A1
Filing date	Jun 24, 2016
Priority date	Mar 15, 2013
Publication date	Nov 3, 2016
Grant date	—

Abstract

Efficient production testing of integrated circuits (ICs). A first production test is implemented on a group of ICs and failures among the test group are assessed. Specifically, the results of the first test are analyzed such that ICs having a recoverable fail and ICs having a non-recoverable fail are differentiated. The ICs are integrated based on the analyzed results and a second production test is implemented. The second production test tests the ICs responsive to the segregation, such that the second production test is limited only to ICs with a recoverable fail. The next succeeding production test will then use the new test program in the second production test with the handler bin designated as having ICs not to be re-tested.

First claim

We claim:

1 . A computer program product for use with integrated circuit testing, the computer program product comprising a computer readable storage medium having computer readable program code embodied therewith, the program code executable by a processor to:
implement a first production test for testing at least one integrated circuit; analyze results of the first test, including differentiating between an integrated circuit with a recoverable fail and an integrated circuit with a non- recoverable fail; segregate each integrated circuit based on the analysis; implement a second production test responsive to the segregation, wherein the second test is implemented on each integrated circuit with a recoverable fail; and assess an accurate segregation of the integrated circuits, and replace the first production test with the second production test as a new test program for a next succeeding production lot of one or more integrated circuits based on the accurate segregation.

2 . The computer program product of claim 1 , further comprising program code to identify a first pass rate of the at least one integrated circuit from the first test and a second pass rate of the at least one integrated circuit from the second test.

3 . The computer program product of claim 2 , further comprising program code to compare the first and second identified pass rates, and determine an accuracy of segregation of the integrated circuits based on the comparison.

4 . The system of claim 3 , wherein the segregation is determined to be accurate in response to the first pass rate exceeding the second pass rate.

5 . The system of claim 3 , wherein the segregation is determined to be inaccurate in response to the second pass rate exceeding the first pass rate.

6 . The computer program product of claim 1 , wherein the segregation includes changing specifications within a handler binning of the first test.

7 . A system comprising:
a processing unit in communication with memory; a functional unit in communication with the processing unit, the functional unit having tools to perform production testing for one or more integrated circuits, the tools comprising:
a first test manager to conduct a first production test on the one or more integrated circuits;
an analysis manager in communication with the first test manager, the analysis manager to analyze results of the first test, and differentiate between an integrated circuit with a recoverable fail and an integrated circuit with a non-recoverable fail;
a segregation manager in communication with the analysis manager, the segregation manager to segregate each integrated circuit based on the analysis;
a second test manager in communication with the segregation manager, the second test manager to implement a second production test in response to the segregation, wherein the second test is implemented on each integrated circuit with a recoverable fail; and
the segregation manager to assess an accurate segregation of the integrated circuits, and to replace the first production test with the second production test as a new test program for a next succeeding production lot of one or more integrated circuits based on the accurate segregation.

8 . The system of claim 7 , further comprising the first test manager to identify a first pass rate of the one or more integrated circuits from the first production test and the second test manager to identify a second pass rate from the one or more integrated circuits from the second production test.

9 . The system of claim 8 , further comprising a confirmation manager to compare the first and second identified pass rates, and determine an accuracy of segregation of the integrated circuits based on the comparison.

10 . The system of claim 9 , wherein the segregation is determined to be accurate in response to the first pass rate exceeding the second pass rate.

11 . The system of claim 9 , wherein the segregation is determined to be inaccurate in response to the second pass rate exceeding the first pass rate.

12 . The system of claim 7 , further comprising the segregation manager to change specifications within a handler binning of the first production test.

13 . A method comprising:
implementing a first production test for testing at least one integrated circuit; analyzing a result of the first test, including differentiating between an integrated circuit with a recoverable fail and an integrated circuit with a non- recoverable fail; segregating each integrated circuit based on the analysis; implementing a second production test responsive to the segregation, wherein the second test is implemented on each integrated circuit with a recoverable fail; and assessing an accurate segregation of the integrated circuits, and replacing the first production test with the second production test as a new test program for a next succeeding production lot of one or more integrated circuits based on the accurate segregation.

14 . The method of claim 13 , further comprising identifying a first pass rate of the at least one integrated circuit from the first test and a second pass rate of the at least one integrated circuit from the second test.

15 . The method of claim 14 , further comprising comparing the first and second identified pass rates, and determining an accuracy of segregation of the integrated circuits based on the comparison.

16 . The method of claim 15 , wherein the segregation is determined to be accurate in response to the first pass rate exceeding the second pass rate.

17 . The method of claim 15 , wherein the segregation is determined to be inaccurate in response to the second pass rate exceeding the first pass rate.

18 . The method of claim 13 , wherein the segregation includes changing specifications within a handler binning of the first test.

Assignees

• IBM

Inventors

• Eng Teck Seng
• Gonzales Michael Russell Uy
• Hermosura Louie Que

Classifications

• G01R31/2832 Primary

  Specific tests of electronic circuits not provided for elsewhere (G01R31/2801, G01R31/316 take precedence) · CPC title

• G01R31/31718

  Logistic aspects, e.g. binning, selection, sorting of devices under test, tester/handler interaction networks, Test management software, e.g. software for test statistics or test evaluation, yield analysis (mechanical aspects G01R31/2808, G01R31/2851) · CPC title

• G01R31/3177 Primary

  Testing of logic operation, e.g. by logic analysers · CPC title

• G01R31/2894 Primary

  Aspects of quality control [QC] (G01R31/31718 takes precedence; program control for QC G05B19/41875) · CPC title