Method, apparatus and system for dynamic bandwidth management in systems

Patent metadata

Field	Value
Publication number	US-2016274187-A1
Application number	US-201514659850-A
Country	US
Kind code	A1
Filing date	Mar 17, 2015
Priority date	Mar 17, 2015
Publication date	Sep 22, 2016
Grant date	—

Abstract

In one embodiment, a bandwidth management controller is coupled to a debug interconnect to dynamically allocate buffer space of a plurality of data buffers to hardware trace information, software trace information, and firmware trace information. The bandwidth management controller further includes a control logic to dynamically control at least one of a voltage and a frequency of the debug interconnect based at least in part on a debug activity level or a functional activity level. Other embodiments are described and claimed.

First claim

What is claimed is:

1 . An apparatus comprising:
a plurality of intellectual property (IP) logic units, each to execute instructions; a debug interconnect coupled to the plurality of IP logic units, the debug interconnect separate from a second interconnect that couples the plurality of IP logic units; a plurality of data buffers coupled to the debug interconnect, the plurality of data buffers to store hardware trace information, software trace information, and firmware trace information; and a bandwidth management controller coupled to the debug interconnect, the bandwidth management controller to dynamically allocate buffer space of the plurality of data buffers to the hardware trace information, the software trace information, and the firmware trace information, the bandwidth management controller further including a control logic to dynamically control at least one of a voltage and a frequency of the debug interconnect based at least in part on a debug activity level.

2 . The apparatus of claim 1 , further comprising a trace controller to receive trace information from the plurality of data buffers and to provide the trace information to one of a plurality of output paths.

3 . The apparatus of claim 1 , wherein the debug interconnect is to communicate functional information between at least some of the plurality of IP logic units during functional operation of the apparatus.

4 . The apparatus of claim 3 , wherein a first IP logic unit includes a control logic to enable the debug interconnect and the plurality of data buffers during the functional operation based on a functional activity level.

5 . The apparatus of claim 1 , further comprising a performance monitoring unit to receive performance monitoring information from at least some of the plurality of IP logic units during debug operation.

6 . The apparatus of claim 5 , wherein the control logic of the bandwidth management controller is to dynamically control the at least one of the voltage and the frequency further based on the performance monitoring information.

7 . The apparatus of claim 1 , wherein the control logic of the bandwidth management controller is to dynamically control the at least one of the voltage and the frequency responsive to a debug-level instruction received from a debug test system coupled to the apparatus.

8 . The apparatus of claim 1 , wherein the bandwidth management controller is to send a backpressure signal to a first input buffer associated with a first IP logic unit to reduce a bandwidth of incoming trace information from the first IP logic unit.

9 . The apparatus of claim 1 , wherein the bandwidth management controller is to disable the debug interconnect during functional operation of the apparatus.

10 . The apparatus of claim 1 , wherein the bandwidth management controller is to send a power reduction signal to a power management unit of the apparatus to enable the power management unit to reduce an activity level of one or more of the plurality of IP logic units during debug operation, wherein the bandwidth management controller is to dynamically control the debug interconnect to operate at a turbo mode level based at least in part on the reduced activity level.

11 . A machine-readable medium having stored thereon data, which if used by at least one machine, causes the at least one machine to fabricate at least one integrated circuit to perform a method comprising:
determining an amount of hardware trace information, software trace information, and firmware trace information being received in a debug unit of the integrated circuit, based at least in part on performance monitoring information received from a plurality of logic units of the integrated circuit; based at least in part on determining the amount, dynamically allocating additional buffer space to a selected one of the hardware trace information, the software trace information, and the firmware trace information; determining a buffer level of buffer space of the debug unit allocated to the selected one trace information; and if the buffer level exceeds a first threshold, dynamically increasing at least one of a voltage and a frequency of a dedicated debug interconnect coupled between the plurality of logic units and the buffer space based thereon.

12 . The machine-readable medium of claim 11 , wherein the method further comprises communicating at least some of the selected one trace information from the buffer space to a debug test system coupled to the integrated circuit.

13 . The machine-readable medium of claim 11 , wherein the method further comprises dynamically increasing the at least one of the voltage and the frequency responsive to a debug-level instruction received from a debug test system coupled to the integrated circuit.

14 . The machine-readable medium of claim 11 , wherein the method further comprises sending a backpressure signal to a first input buffer associated with a first logic unit to reduce a bandwidth of incoming trace information from the first logic unit.

15 . The machine-readable medium of claim 11 , wherein the method further comprises enabling the integrated circuit to operate at one or more of a voltage and a frequency higher than a device specification during debug operation, under control of a debug test system coupled to the integrated circuit.

16 . A system comprising:
at least one core to independently execute instructions; at least one intellectual property (IP) logic to independently perform operations; a first interconnect coupled to the at least one core and the at least one IP logic; and a debug unit coupled to the at least one core and the at least one IP logic, the debug unit including:
a debug interconnect;
a plurality of buffers to store hardware trace information, software trace information, and firmware trace information in a debug mode and to store functional information in a functional mode; and
a control logic to dynamically allocate the plurality of buffers to the hardware trace information, the software trace information, and the firmware trace information in the debug mode based at least in part on performance monitoring information received from the at least one core and the at least one IP logic, wherein the control logic is to dynamically control a frequency and a voltage of the debug unit in the debug mode based at least in part on a buffer level consumed by at least one of the hardware trace information, the software trace information, and the firmware trace information.

17 . The system of claim 16 , wherein the control logic is to dynamically increase allocation of the plurality of buffers for the hardware trace information responsive to a starvation signal received from a master of the hardware trace information.

18 . The system of claim 17 , wherein the control logic is to limit the dynamic increase to a configured maximum level, the configured maximum level received from a debug test system coupled to the system, the system comprising a system on chip (SoC).

19 . The system of claim 18 , wherein the control logic is to enable the functional information to be communicated via the debug interconnect in the functional mode of the SoC.

20 . The system of claim 16 , wherein the control logic is to enable the debug interconnect to operate at one or more of a voltage and a frequency higher than a device specification during the debug mode, under control of a debug test system coupled to the system.

21 . The system of claim 16 , further comprisin

Assignees

• Intel Corp

Inventors

• Menon Sankaran M
• Trp Babu
• Kuehnis Rolf

Classifications

• G01R31/3177

  Testing of logic operation, e.g. by logic analysers · CPC title

• G06F11/3648

  using additional hardware · CPC title

• G06F11/348

  Circuit details, i.e. tracer hardware · CPC title

• G06F11/3466

  Performance evaluation by tracing or monitoring · CPC title

• G06F2201/88

  Monitoring involving counting · CPC title