Photolithography systems and associated methods of overlay error correction

Patent metadata

Field	Value
Publication number	US-9195149-B2
Application number	US-201213598467-A
Country	US
Kind code	B2
Filing date	Aug 29, 2012
Priority date	Nov 6, 2008
Publication date	Nov 24, 2015
Grant date	Nov 24, 2015

Abstract

Several embodiments of photolithography systems and associated methods of overlay error correction are disclosed herein. In one embodiment, a method for correcting overlay errors in a photolithography system includes measuring a plurality of first overlay errors that individually correspond to a microelectronic substrate in a first batch of microelectronic substrates. The method also includes determining a relationship between the first overlay errors and a first sequence of the microelectronic substrates in the first batch. The method further includes correcting a second overlay error of individual microelectronic substrates in a second batch based on a second sequence of the microelectronic substrates in the second batch and the determined relationship.

First claim

I claim:

1. A photolithography system, comprising:
a substrate support configured to individually carry a first batch of microelectronic substrates;
a metrology tool configured to measure a plurality of overlay errors individually corresponding to one of the microelectronic substrates in the first batch; and
a controller operatively coupled to the metrology tool, the controller having a computer-readable storage medium containing instructions for performing a process comprising:
receiving the overlay errors of the individual microelectronic substrates in the first batch from the metrology tool;
describing a relationship between the overlay errors and a sequence of the microelectronic substrates in a mathematical model;
storing the mathematical model in the computer-readable storage medium; and
processing a second batch of microelectronic substrates using the mathematical model.

2. The photolithography system of claim 1 wherein receiving the overlay errors includes receiving at least one of an X-translation, a Y-translation, a substrate rotation, a substrate orthogonality, a field magnification, an asymmetrical magnification, a field rotation, a field asymmetrical rotation, a substrate expansion along the X-axis, and/or a substrate expansion along the Y-axis of the individual microelectronic substrates in the first batch.

3. The photolithography system of claim 1 wherein the computer-readable storage medium of the controller contains instructions for performing a process comprising:
determining a sequence of the microelectronic substrates in the second batch;
retrieving the mathematical model from the computer-readable storage medium; and
determining an overlay correction parameter for at least one of the microelectronic substrates in the second batch based on the determined sequence and the retrieved mathematical model.

4. The photolithography system of claim 1 wherein the computer-readable storage medium of the controller contains instructions for performing a process comprising:
receiving overlay errors of the individual microelectronic substrates in the second batch from the metrology tool; and
updating the relationship between the overlay errors and the sequence of the microelectronic substrates in the mathematical model.

5. The photolithography system of claim 1 wherein the computer-readable storage medium of the controller contains instructions for performing a process comprising:
receiving overlay errors of the individual microelectronic substrates in the second batch from the metrology tool;
updating the relationship between the overlay errors and the sequence of the microelectronic substrates in the mathematical model;
determining a sequence of microelectronic substrates in a third batch;
retrieving the updated mathematical model from the computer-readable storage medium; and
determining an overlay correction parameter for the microelectronic substrate based on the determined sequence and the updated mathematical model.

6. The photolithography system of claim 1 wherein the computer-readable storage medium of the controller further contains instructions for correcting a second overlay error of individual microelectronic substrates in the second batch based on a second sequence of the microelectronic substrates in the second batch corresponding to a first sequence of the microelectronic substrates in the first batch such that the correction of the second overlay error of the individual microelectronic substrates in the second batch are based on the measurement of a corresponding microelectronic substrate in the first batch, and a relationship between the first overlay errors and the first sequence of the microelectronic substrates in the first batch.

7. The photolithography system of claim 1 wherein the computer-readable storage medium further includes instructions correcting at least one overlay error of corresponding microelectronic substrate in the second batch that have the same sequence number as the microelectronic substrate in the first batch based on using the mathematical model.

8. The photolithography system of claim 1 wherein processing the second batch of microelectronic substrates includes:
receiving sequence information about the microelectronic substrates in the second batch; and
determining a correction parameter for processing each microelectronic substrate in the second batch based on the sequence information and the mathematical model.

9. A system, comprising:
a metrology tool configured to provide overlay errors associated with microelectronic substrates; and
a computer system configured to be in communication with the metrology tool, the computer system comprising
a processor;
a computer-readable storage medium operatively coupled to the processor, the computer-readable storage medium containing instructions for performing a process comprising:
receiving a set of overlay errors in which individual overlay errors correspond to an individual microelectronic substrate in a set of microelectronic substrates;

computing a mathematical model based on the overlay errors and a sequence of the microelectronic substrates to correct overlay errors of subsequently processed microelectronic substrates based on the received set of overlay errors of the individual microelectronic substrates in the set of microelectronic substrates; and
storing the mathematical model in the computer-readable storage medium.

10. The system of claim 9 wherein receiving the set of overlay errors includes receiving at least one of an X-translation, a Y-translation, a substrate rotation, a substrate orthogonality, a field magnification, an asymmetrical magnification, a field rotation, a field asymmetrical rotation, a substrate expansion along the X-axis, and/or a substrate expansion along the Y-axis of the individual microelectronic substrates in the set.

11. The system of claim 9 wherein the set of microelectronic substrates are a first plurality of microelectronic substrates, and wherein the computer-readable storage medium contains instructions for performing a process comprising:
retrieving the mathematical model computed based on the overlay error and the sequence of the first plurality of microelectronic substrates; and
calculating an overlay correction parameter for a microelectronic substrate based on the retrieved mathematical model and a sequence of microelectronic substrates in a second plurality of microelectronic substrates.

12. The system of claim 9 wherein the set of microelectronic substrates are a first plurality of microelectronic substrates, and wherein the set of overlay errors is a first set of overlay errors, and further wherein the computer-readable storage medium contains instructions for performing a process comprising:
receiving a second set of overlay errors of individual microelectronic substrates in a second plurality of microelectronic substrates;
purging the computed mathematical model based on the first set of overlay errors from the computer-readable storage medium;
computing a new mathematical model based on the second set of overlay errors and a sequence of the second plurality of microelectronic substrates; and
storing the new mathematical model in the computer-readable storage medium.

13. The system of claim 9 wherein the set of microelectronic substrates are a first plurality of microelectronic substrates, and wherein the set of overlay errors is a first set of overlay errors, and further wherein the computer-readable storage medium contains instructions for performing a process comprising:
receiving a second set of overlay errors of individual microelectronic substrates in a

Assignees

• Chung Woong Jae
• Micron Technology Inc

Inventors

• Chung Woong Jae

Classifications

• G03B27/52 Primary

  Details · CPC title

• G03F7/70633 Primary

  Overlay, i.e. relative alignment between patterns printed by separate exposures in different layers, or in the same layer in multiple exposures or stitching · CPC title

• G05B2219/45031

  Manufacturing semiconductor wafers · CPC title

• G05B19/41875 Primary

  characterised by quality surveillance of production · CPC title

• G05B2219/42155

  Model · CPC title