Methods for forming recesses in source/drain regions and devices formed thereof
US-12132089-B2 · Oct 29, 2024 · US
Etch process for reducing directed self assembly pattern defectivity
US8945408B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8945408-B2 |
| Application number | US-201313918794-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jun 14, 2013 |
| Priority date | Jun 14, 2013 |
| Publication date | Feb 3, 2015 |
| Grant date | Feb 3, 2015 |
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Abstract
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Provided is a method for preparing a patterned directed self-assembly layer, comprising: providing a substrate having a block copolymer layer comprising a first phase-separated polymer defining a first pattern in the block copolymer layer and a second phase-separated polymer defining a second pattern in the block copolymer layer; and performing an etching process to selectively remove the second phase-separated polymer while leaving behind the first pattern of the first phase-separated polymer on the surface of the substrate, the etching process being performed at a substrate temperature less than or equal to about 20 degrees C. The method further comprises providing a substrate holder for supporting the substrate, the substrate holder having a first temperature control element for controlling a first temperature at a central region and second temperature control element at an edge region of the substrate and setting a target value for the first and the second temperature.
First claim
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What is claimed is: 1. A method for preparing a patterned directed self-assembly (DSA) layer, comprising: providing a substrate having a block copolymer layer on a surface thereof, said block copolymer layer comprising a first phase-separated polymer defining a first pattern in said block copolymer layer and a second phase-separated polymer defining a second pattern in said block copolymer layer; selecting defined values of pattern defectivity for preventing pattern collapse for…
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Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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- What does patent US8945408B2 cover?
- Provided is a method for preparing a patterned directed self-assembly layer, comprising: providing a substrate having a block copolymer layer comprising a first phase-separated polymer defining a first pattern in the block copolymer layer and a second phase-separated polymer defining a second pattern in the block copolymer layer; and performing an etching process to selectively remove the secon…
- Who is the assignee on this patent?
- Tokyo Electron Ltd
- What technology area does this patent fall under?
- Primary CPC classification H10P50/287. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Feb 03 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).