Integration method of vertical dram with periphery circuit

Patent metadata

Field	Value
Publication number	US-2026047070-A1
Application number	US-202418795822-A
Country	US
Kind code	A1
Filing date	Aug 6, 2024
Priority date	Aug 6, 2024
Publication date	Feb 12, 2026
Grant date	—

Abstract

A semiconductor device including a transistor region including vertical transistors arranged in an array to form a memory array area, and word lines connected to the vertical transistors. A capacitor region is formed within the memory array area above the transistor region and including vertical capacitors vertically connected to the vertical transistors through capacitor contacts. Bit lines are formed below the transistor region and vertically connected to the vertical transistors, the word lines and bit lines being arranged to form a matrix configuration within the memory array area. Backside contacts are formed within the memory array area, each backside contact connected to either a respective word line or a respective bit line and extending vertically to below the bit lines.

First claim

What is claimed is:

1 . A semiconductor device, comprising:
a transistor region comprising vertical transistors arranged in an array to form a memory array area, and word lines connected to the vertical transistors; a capacitor region formed within the memory array area above the transistor region and comprising vertical capacitors vertically connected to the vertical transistors through capacitor contacts; bit lines formed below the transistor region and vertically connected to the vertical transistors, wherein the word lines and bit lines are arranged to form a matrix configuration within the memory array area; and backside contacts formed within the memory array area, each backside contact connected to either a respective word line or a respective bit line and extending vertically to below the bit lines.

2 . The semiconductor device of claim 1 , wherein the vertical transistors comprise Gate All Around (GAA) transistors arranged in an array.

3 . The semiconductor device of claim 2 , wherein each word line is connected to gate structures of adjacent GAA transistors.

4 . The semiconductor device of claim 1 , wherein the bit lines and word lines have a pitch of approximately 30-40 nm.

5 . The semiconductor device of claim 1 , wherein the backside contacts comprise at least one word line contact connected to a respective word line and extending vertically to pass through in-between two adjacent bit lines.

6 . The semiconductor device of claim 1 , wherein the backside contacts comprise:
a plurality of word line contacts formed within the memory array area, each word line contact being connected to a respective word line and extending vertically to below the bit lines; and a plurality of bit line contacts formed within the memory array area, each bit line contact being connected to a respective bit line and extending vertically to below the bit lines.

7 . The semiconductor device of claim 6 , further comprising a plurality of wafer bonding pads formed within the memory array area below the backside contacts, each wafer bonding pad being connected to a respective word line contact or bit line contact.

8 . The semiconductor device of claim 7 , wherein each of the wafer bonding pads comprises at least one of copper (Cu), aluminum (Al), or tungsten (W).

9 . The semiconductor device of claim 7 , wherein each of the wafer bonding pads has a diameter of approximately 0.5 μm or less.

10 . The semiconductor device of claim 7 , further comprising a peripheral circuit wafer which is hybrid bonded to a surface including the wafer bonding pads, the peripheral circuit wafer comprising a plurality of peripheral circuit components connected to the word line contacts and bit line contacts through the wafer bonding pads.

11 . The semiconductor device of claim 1 , further comprising:
a peripheral circuit wafer comprising a plurality of peripheral circuit components; and a hybrid bod interface which connects the peripheral circuit wafer to a wafer including the backside contacts such that the peripheral circuit components are electrically connected to the backside contacts.

12 . The semiconductor device of claim 11 wherein the device is a 4F 2 dynamic random-access memory (DRAM) device.

13 . A method of forming a semiconductor device, comprising:
providing a memory circuit wafer comprising:
a transistor region comprising vertical transistors arranged in a memory array area and word lines connected to the vertical transistors,
a capacitor region formed in the memory array area above the transistor region and comprising vertical capacitors vertically connected to the vertical transistors through capacitor contacts, and
bit lines formed below the transistor region and vertically connected to the vertical transistors, wherein the word lines and bit lines are arranged to form a matrix configuration within the memory array area; and
forming a plurality of backside contacts formed within the memory array area, each backside contact being connected to either a respective word line or a respective bit line and extending vertically to below the bit lines.

14 . The method of claim 13 , wherein the forming word line contacts comprises forming at least one word line contact that passes through in-between two adjacent bit lines.

15 . The method of claim 14 , wherein the forming at least one word line contact comprises performing a self-aligned contact (SAC) etch process to form the at least one word line contact.

16 . The method of claim 15 , wherein the SAC etch process comprises forming a hole having a diameter of approximately 15-20 nm.

17 . The method of claim 13 , further comprising forming a plurality of wafer bonding pads within the memory array area below the backside contacts, each wafer bonding pad being connected to a respective backside contact.

18 . The method of claim 17 , wherein the forming bonding pads comprises forming bonding pads each having a diameter of less than 0.5 μm.

19 . The method of claim 17 , further comprising:
providing a peripheral circuit wafer comprising peripheral circuit components; and hybrid bonding the peripheral circuit wafer to the memory circuit wafer below the backside contacts such that the peripheral circuit components are electrically connected to the backside contacts.

20 . The method of claim 13 , wherein the semiconductor device is a 4F 2 dynamic random-access memory (DRAM) device.

21 . The semiconductor device of claim 1 , wherein the vertical transistors comprise double-gate vertical transistors arranged in an array.

Assignees

• Tokyo Electron Ltd

Inventors

• Lee Sunghil
• Chae Soo Doo
• Kim Hojin
• Lu Yen-Tien
• Sitaram Arkalgud R

Classifications

• H10D30/6735

  having gates fully surrounding the channels, e.g. gate-all-around · CPC title

• H10D30/6728

  Vertical TFTs · CPC title

• H10B12/05

  Making the transistor · CPC title

• H10W72/923

  Bond pads having multiple stacked layers · CPC title

• H10B12/482

  Bit lines · CPC title