Fabricating three-dimensional semiconductor structures
US-12598747-B2 · Apr 7, 2026 · US
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Kim Hojin patents
Kim Hojin is listed as an inventor on 26 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Kim Hojin |
| Total patents | 26 |
| First publication | Jun 25, 2020 |
| Latest publication | Apr 7, 2026 |
Notable patents
Publications ranked by popularity score, then publication date.
Next generation bonding layer for 3D heterogeneous integration
US-12577665-B2 · Mar 17, 2026 · US
Methods to improve etch selectivity and critical dimension uniformity when etching high aspect ratio features within a hard mask layer
US-2026068612-A1 · Mar 5, 2026 · US
Integration method of vertical dram with periphery circuit
US-2026047070-A1 · Feb 12, 2026 · US
Polymer coatings for solid supports
US-2026028582-A1 · Jan 29, 2026 · US
Methods for fabricating isolation structures using directional beam process
US-12538560-B2 · Jan 27, 2026 · US
Integration method of vertical dram with peripheral circuit
US-2025311241-A1 · Oct 2, 2025 · US
Plasma assisted metal oxide reduction
US-2025300007-A1 · Sep 25, 2025 · US
Method for etching a pattern in a layer of a substrate
US-2025253157-A1 · Aug 7, 2025 · US
Contact patterning
US-2025246481-A1 · Jul 31, 2025 · US
Recent patents
Latest publications not already listed above.
Layer stack for extreme ultraviolet lithography
US-2025164891-A1 · May 22, 2025 · US
Method of surface modification for wafer bonding
US-2025087628-A1 · Mar 13, 2025 · US
Fabricating three-dimensional semiconductor structures
US-12193231-B2 · Jan 7, 2025 · US
Selective etching with fluorine, oxygen and noble gas containing plasmas
US-12131914-B2 · Oct 29, 2024 · US
Stress relief in semiconductor wafers
US-11990425-B2 · May 21, 2024 · US
Fabricating three-dimensional semiconductor structures
US-2024147719-A1 · May 2, 2024 · US
Methods for fabricating isolation structures using directional beam process
US-2024145312-A1 · May 2, 2024 · US
Methods for forming semiconductor devices with isolation structures
US-2024071808-A1 · Feb 29, 2024 · US
Plasma surface treatment for wafer bonding methods
US-2024071746-A1 · Feb 29, 2024 · US
Next generation bonding layer for 3d heterogeneous integration
US-2024071984-A1 · Feb 29, 2024 · US
Wafer bonding method using selective deposition and surface treatment
US-2023075263-A1 · Mar 9, 2023 · US
Selective Etching with Fluorine, Oxygen and Noble Gas Containing Plasmas
US-2022199418-A1 · Jun 23, 2022 · US
Fabricating three-dimensional semiconductor structures
US-2022115399-A1 · Apr 14, 2022 · US
Stress Relief in Semiconductor Wafers
US-2022102289-A1 · Mar 31, 2022 · US
System and method employing three-dimensional (3D) emulation of in-kerf optical macros
US-10733354-B2 · Aug 4, 2020 · US
Design system and method employing three-dimensional (3d) emulation of in-kerf optical macros
US-2020201955-A1 · Jun 25, 2020 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Tokyo Electron Ltd | 23 |
| Globalfoundries Inc | 2 |
| Univ Orleans | 2 |
| Singular Genomics Systems Inc | 1 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| H10W80/327 | 5 |
| H10W10/17 | 5 |
| H10W10/014 | 5 |
| H01L21/76224 | 5 |
| H10B43/27 | 5 |