3D Compatible 2 Transistor-n Capacitor Ferroelectric Random Access Memory with Quasi-Nondestructive Readout Characteristics

Patent metadata

Field	Value
Publication number	US-2025372141-A1
Application number	US-202418680191-A
Country	US
Kind code	A1
Filing date	May 31, 2024
Priority date	May 31, 2024
Publication date	Dec 4, 2025
Grant date	—

Abstract

Embodiments can relate to techniques for sensing capacitor polarization in a random access memory (RAM) cell by: applying a read gate bias to a transistor; allowing or causing ferroelectric polarization (PFE) of a capacitor to set a threshold voltage (VTH); and performing a read operation by sensing polarization in a capacitor. Performing the read operation can occur in a quasi-nondestructive manner due to the structure of the RAM cell, which can include: plural capacitors connected to node 1, each individual capacitor also connected to an individual write bit line (WBL); a write transistor (TW) connected to: node 1, a write word line (WWL), and a write plate line (WPL); and a read transistor (TR) connected to: node 1, a read bit line (RBL), and a read source line (RSL). The RAM cell allows for performing plural read operations without a write-back operation to restore polarization in a capacitor.

First claim

What is claimed is:

1 . A random access memory (RAM) cell, comprising:
plural capacitors connected to node 1 , each individual capacitor connected to an individual write bit line (WBL); a write transistor (T W ) connected to: node 1 , a write word line (WWL), and a write plate line (WPL); and a read transistor (T R ) connected to: node 1 , a read bit line (RBL), and a read source line (RSL).

2 . The RAM cell of claim 1 , wherein:
the RAM cell is a 2 Transistor-n Capacitor (2TnC) cell.

3 . The RAM cell of claim 1 , further comprising:
one or more voltage sources connected to each WBL, the WWL, the WPL, the RBL and/or the RSL.

4 . The RAM cell of claim 3 , wherein:
the one or more voltage sources is configured to generate one or more voltage pulses.

5 . The RAM cell of claim 1 , wherein:
one or more capacitors is a metal-ferroelectric-metal (MFM) capacitor.

6 . The RAM cell of claim 1 , wherein:
the T W and/or the T R is a field-effect-transistor (FET).

7 . A method for sensing capacitor polarization in a random access memory (RAM) cell, the method comprising:
applying a read gate bias to a transistor of the RAM cell; allowing or causing ferroelectric polarization (P FE ) of a capacitor to set a threshold voltage (V TH ) for the RAM cell; performing a read operation by sensing polarization in a capacitor of the RAM cell.

8 . The method of claim 7 , wherein:
performing the read operation occurs in a quasi-nondestructive manner.

9 . The method of claim 7 , wherein the RAM cell includes: plural capacitors connected to node 1 , each individual capacitor connected to an individual write bit line (WBL); a write transistor (T W ) connected to node 1 , connected to a write word line (WWL), and connected to a write plate line (WPL); and a read transistor (T R ) connected to node 1 , connect to a read bit line (RBL), and connected to a read source line (RSL), wherein:
performing the read operation involves turning OFF the T W , applying a read voltage (V R ) to the W BL , and sensing T R current.

10 . The method of claim 7 , further comprising:
performing plural read operations without a write-back operation to restore polarization in the capacitor.

11 . The method of claim 9 , further comprising:
generating separate read and write paths by:
performing a write operation to turn ON T W ;
generating a first operating state for the RAM cell by applying: one or more voltage pulses (VWBL) to one or more capacitors; and one or more voltage pulses (VWPL) to the T W ; and/or
generating a second operating state for the RAM cell by applying: one or more voltage pulses (VWBL) to one or more capacitors; and one or more voltage pulses (VWPL) to the T W .

12 . The method of claim 11 , further comprising:
performing plural read operations before accumulative P FE switching leads to destruction of the first state or the second state.

13 . The method of claim 7 , wherein:
the RAM cell is a 2 Transistor-n Capacitor (2TnC) cell.

14 . The method of claim 9 , wherein:
one or more capacitors is a metal-ferroelectric-metal (MFM) capacitor.

15 . The method of claim 9 , wherein:
the T W and/or the T R is a field-effect-transistor (FET).

Assignees

• Penn State Res Found

Inventors

• Xiao Yi
• Deng Shan
• Narayanan Vijaykrishnan
• Ni Kai

Classifications

• G11C11/2273 Primary

  Reading or sensing circuits or methods · CPC title

• G11C11/221

  using ferroelectric capacitors · CPC title

• G11C11/2275 Primary

  Writing or programming circuits or methods · CPC title