Gain cell using planar and trench ferroelectric and anti-ferroelectric capacitors for edram

Patent metadata

Field	Value
Publication number	US-2024114697-A1
Application number	US-202217958279-A
Country	US
Kind code	A1
Filing date	Sep 30, 2022
Priority date	Sep 30, 2022
Publication date	Apr 4, 2024
Grant date	—

Abstract

Embodiments disclosed herein include a memory device. In an embodiment, the memory device comprises a first transistor, where the first transistor is an access transistor to write data. In an embodiment, the memory device further comprises a ferroelectric capacitor for storing data. In an embodiment, the memory device further comprises a second transistor, where the second transistor is a sense transistor to read the data stored on the ferroelectric capacitor.

First claim

What is claimed is:

1 . A memory device, comprising:
a first transistor, wherein the first transistor is an access transistor to write data; a ferroelectric capacitor for storing data; and a second transistor, wherein the second transistor is a sense transistor to read the data stored on the ferroelectric capacitor.

2 . The memory device of claim 1 , wherein the first transistor, the second transistor, and the ferroelectric capacitor are coupled together by a node.

3 . The memory device of claim 2 , wherein the node is coupled to a terminal of the ferroelectric capacitor, a drain of the first transistor and a gate of the second transistor.

4 . The memory device of claim 1 , wherein the ferroelectric capacitor comprises hafnium, zirconium, and oxygen, or perovskite materials, or aluminum, scandium, and nitrogen.

5 . The memory device of claim 1 , wherein the ferroelectric capacitor is a planar capacitor.

6 . The memory device of claim 1 , wherein the ferroelectric capacitor is a trench capacitor.

7 . The memory device of claim 1 , wherein the ferroelectric capacitor is coupled to a plate line.

8 . The memory device of claim 1 , wherein a gate of the first transistor is coupled to a write word line, and wherein a drain of the first transistor is coupled to a write bit line.

9 . The memory device of claim 1 , wherein a source of the second transistor is coupled to a read word line, and wherein a drain of the second transistor is coupled to a read bit line.

10 . The memory device of claim 1 , wherein the ferroelectric capacitor is stacked above the first transistor and the second transistor.

11 . The memory device of claim 10 , wherein the ferroelectric capacitor is directly over the first transistor.

12 . The memory device of claim 1 , wherein the first transistor is laterally adjacent to the second transistor.

13 . The memory device of claim 1 , wherein the first transistor and the second transistor are planar, fin-based transistors, nanowire-based transistors, nanoribbon-based transistors, or nanosheet-based transistors.

14 . A memory device comprising:
a semiconductor fin; a first transistor formed on the semiconductor fin; a second transistor formed on the semiconductor fin adjacent to the first transistor; a ferroelectric capacitor over the first transistor; and a node to electrically couple the first transistor, the second transistor, and the ferroelectric capacitor together.

15 . The memory device of claim 14 , wherein the node is coupled to a terminal of the ferroelectric capacitor, a drain of the first transistor, and a gate of the second transistor.

16 . The memory device of claim 14 , wherein the first transistor is a write transistor, and wherein the second transistor is a read transistor.

17 . The memory device of claim 14 , wherein the ferroelectric capacitor comprises hafnium, zirconium, and oxygen, or perovskite materials, or aluminum, scandium, and nitrogen.

18 . A computing system, comprising:
a board; a device coupled to the board, wherein the device comprises a memory structure, wherein the memory structure, comprises:
an access transistor;
a sense transistor adjacent to the access transistor; and
a ferroelectric capacitor, wherein the ferroelectric capacitor is over the access transistor and the sense transistor.

19 . The computing system of claim 18 , further comprising:
a processor coupled to the board.

20 . The computing system of claim 18 , further comprising:
a communication chip coupled to the board.

Assignees

• Intel Corp

Inventors

• Shivaraman Shriram
• Chang Sou-Chi
• Dutta Sourav
• Avci Uygar E

Classifications

• H01L27/11507 Primary

  Electricity · mapped topic

• H10B53/30 Primary

  characterised by the memory core region · CPC title