Gain cell semiconductor memory device and driving method thereof

Patent metadata

Field	Value
Publication number	US-9443844-B2
Application number	US-201213461807-A
Country	US
Kind code	B2
Filing date	May 2, 2012
Priority date	May 10, 2011
Publication date	Sep 13, 2016
Grant date	Sep 13, 2016

Abstract

A memory cell including two transistors and one capacitor, which is known as a gain cell, is improved. One electrode of the capacitor is connected to a bit line, and the other electrode thereof is connected to a drain of a write transistor. A source of the write transistor is connected to a source line. As a result, for example, in the case where a stacked capacitor is used, the one electrode of the capacitor can be part of the bit line. Only one specific write transistor is turned on when a potential of the source line and a potential of the write bit line are set; thus, only one memory cell can be rewritten.

First claim

What is claimed is:

1. A semiconductor device comprising:
a write bit line;
a write word line intersecting with the write bit line;
a read line;
a source line intersecting with the read line; and
a memory cell,
wherein the memory cell comprises a write transistor, a read transistor, and a capacitor,
wherein a gate, a drain, and a source of the write transistor are connected to the write word line, one electrode of the capacitor, and the source line, respectively,
wherein a gate, a drain, and a source of the read transistor are connected to the drain of the write transistor, the read line, and the source line, respectively,
wherein the other electrode of the capacitor is connected to the write bit line,
wherein a potential corresponding to a piece of data to be stored in the memory cell is configured to be supplied to the write bit line, and
wherein the potential of the write bit line is configured to be changed when the piece of data stored in the memory cell is rewritten.

2. The semiconductor device according to claim 1 , wherein the source line is formed in parallel to the write word line.

3. The semiconductor device according to claim 1 , wherein a conductivity type of the write transistor is different from a conductivity type of the read transistor.

4. The semiconductor device according to claim 1 , wherein off-state resistance of the write transistor is higher than or equal to 1×10 18 Ω.

5. A semiconductor device comprising:
a write bit line;
a write word line intersecting with the write bit line;
a read line;
a source line intersecting with the read line; and
a memory cell,
wherein the memory cell comprises a write transistor, a read transistor, and a capacitor,
wherein a gate, a drain, and a source of the write transistor are connected to the write word line, one electrode of the capacitor, and the source line, respectively,
wherein the other electrode of the capacitor is connected to the write bit line,
wherein a gate, a drain, and a source of the read transistor are connected to the drain of the write transistor, the read line, and the source line, respectively,
wherein the source line is in parallel to the write bit line,
wherein a potential corresponding to a piece of data to be stored in the memory cell is configured to be supplied to the write bit line, and
wherein the potential of the write bit line is configured to be changed when the piece of data stored in the memory cell is rewritten.

6. The semiconductor device according to claim 5 , wherein a conductivity type of the write transistor is different from a conductivity type of the read transistor.

7. The semiconductor device according to claim 5 , wherein off-state resistance of the write transistor is higher than or equal to 1×10 18 Ω.

8. A method for driving a semiconductor device, the semiconductor device comprising:
a write bit line;
a write word line intersecting with the write bit line;
a read line;
a source line intersecting with the read line; and
a memory cell,
wherein the memory cell comprises a write transistor, a read transistor, and a capacitor,
wherein a gate, a drain, and a source of the write transistor are connected to the write word line, one electrode of the capacitor, and the source line, respectively,
wherein a gate, a drain, and a source of the read transistor are connected to the drain of the write transistor, the read line, and the source line, respectively,
wherein the other electrode of the capacitor is connected to the write bit line,
wherein a potential corresponding to a piece of data to be stored in the memory cell is configured to be supplied to the write bit line,
wherein the potential of the write bit line is configured to be changed when the piece of data stored in the memory cell is rewritten, and
wherein a potential of the source line is kept constant during data reading and data writing.

9. The method for driving the semiconductor device according to claim 8 , wherein the source line is formed in parallel to the write word line.

10. The method for driving the semiconductor device according to claim 8 , wherein a conductivity type of the write transistor is different from a conductivity type of the read transistor.

11. The method for driving the semiconductor device according to claim 8 , wherein off-state resistance of the write transistor is higher than or equal to 1×10 18 Ω.

12. A method for driving a semiconductor device, the semiconductor device comprising:
a write bit line;
a write word line intersecting with the write bit line;
a read line;
a source line intersecting with the read line; and
a memory cell,
wherein the memory cell comprises a write transistor, a read transistor, and a capacitor,
wherein a gate, a drain, and a source of the write transistor are connected to the write word line, one electrode of the capacitor, and the source line, respectively,
wherein a gate, a drain, and a source of the read transistor are connected to the drain of the write transistor, the read line, and the source line, respectively,
wherein the other electrode of the capacitor is connected to the write bit line,
wherein a potential corresponding to a piece of data to be stored in the memory cell is configured to be supplied to the write bit line,
wherein the potential of the write bit line is configured to be changed when the piece of data stored in the memory cell is rewritten, and
wherein potentials of the drain and the source of the write transistor immediately after writing of the piece of data are equal to potentials of the drain and the source of the write transistor immediately after writing of another piece of data.

13. The method for driving the semiconductor device according to claim 12 , wherein the source line is formed in parallel to the write word line.

14. The method for driving the semiconductor device according to claim 12 , wherein a conductivity type of the write transistor is different from a conductivity type of the read transistor.

15. The method for driving the semiconductor device according to claim 12 , wherein off-state resistance of the write transistor is higher than or equal to 1×10 18 Ω.

16. A method for driving a semiconductor device, the semiconductor device comprising:
a write bit line;
a write word line intersecting with the write bit line;
a read line;
a source line intersecting with the read line; and
a memory cell,
wherein the memory cell comprises a write transistor, a read transistor, and a capacitor,
wherein a gate, a drain, and a source of the write transistor are connected to the write word line, one electrode of the capacitor, and the source line, respectively,
wherein the other electrode of the capacitor is connected to the write bit line,
wherein a gate, a drain, and a source of the read transistor are connected to the drain of the write transistor, the read line, and the source line, respectively,
wherein the source line is in parallel to the write bit line,
wherein a potential corresponding to a piece of data to be stored in the memory cell is configured to be supplied to the write bit line,
wherein the potential of the write bit line is configured to be changed when the piece of data stored in the memory cell is rewritten, and
wherein a potential of the source line is kept constant during data reading and data writing.

17. The method for driving the semiconductor device according to claim 16 , wherein a conductivity type of the write transistor is different from a conductivity type of the read transistor.

18. The method for dr

Assignees

• Takemura Yasuhiko
• Semiconductor Energy Lab

Inventors

• Takemura Yasuhiko

Classifications

• H10D87/00

  Integrated devices comprising both bulk components and either SOI or SOS components on the same substrate · CPC title

• H10D88/00 Primary

  Three-dimensional [3D] integrated devices · CPC title

• H01L27/108

  Electricity · mapped topic

• H01L27/1207

  Electricity · mapped topic

• G11C11/405

  with three charge-transfer gates, e.g. MOS transistors, per cell · CPC title