Gate driver circuit and process for reducing dead time duration upon switching

Patent metadata

Field	Value
Publication number	US-2025330166-A1
Application number	US-202319122089-A
Country	US
Kind code	A1
Filing date	Jul 7, 2023
Priority date	Nov 10, 2022
Publication date	Oct 23, 2025
Grant date	—

Abstract

Gate driver circuit, for a half bridge of a converter where a first switching device and a second switching device are controlled independently and in a complementary way comprising a first gate current mirroring circuit on a sink branch of a first gate driver buffer and a second gate current mirroring circuit on a sink branch of a second gate driver buffer to provide, in advance from pulse signals issued from the controller, a first early gate pullup command signal issuing from the first gate current mirroring circuit, for the second gate driver buffer under a turning off of a first switching device and a second early gate pullup command signal issuing from the second gate current mirroring circuit, for the first gate driver buffer from a turning off of a second switching device, in advance from gate pull up pulse signals issued from the controller.

First claim

1 . A gate driver circuit, for a half bridge of a converter where a first switching device, having a first gate, and a second switching device, having a second gate, are controlled independently and in a complementary way respectively through a first gate driver buffer and a second gate driver buffer, and a controller providing gate pull up and gate pull down pulse signals to the first and second gate drivers buffers, characterized in that it comprises a first gate current mirroring circuit on a sink branch of said first gate driver buffer and a second gate current mirroring circuit on a sink branch of said second gate driver buffer to provide, in advance from said pulse signals issued from the controller, a first early gate pullup command signal issuing from the first gate current mirroring circuit, for the second gate driver buffer under a turning off of said first switching device and a second early gate pullup command signal issuing from the second gate current mirroring circuit, for the first gate driver buffer from a turning off of said second switching device, in advance from gate pull up pulse signals issued from the controller.

2 . The gate driver circuit according to claim 1 , wherein the gate drivers buffers associated to the current mirroring circuits are driven by pre-driver circuits transferring control signals from the controller to the gate drivers buffers and providing a first galvanic insulation between said controller and said gate drivers buffers.

3 . The gate driver circuit according to claim 1 , wherein said early gate pullup command signals of the first gate mirroring circuit and the second gate mirroring circuit are transferred respectively to the second gate driver buffer and to the first gate driver buffer through second galvanic insulation means.

4 . The gate driver circuit according to claim 3 , comprising for each gate driver buffer, a mixer circuit where said early gate pullup command signal is combined with the gate pulse signal issued from said pre-driver after said second galvanic insulation means.

5 . The gate driver circuit according to claim 1 , comprising conditioning and/or amplifier means of said early command signals.

6 . The gate driver circuit according to claim 1 , comprising a reset circuit which is configured to reset the early gate pullup command signal upon occurrence of the gate pull up pulse signals issued from the controller.

7 . A process for reducing the dead time duration upon switching of switches in a half bridge of a converter comprising sensing of a gate current in a gate driver circuit during an on to off switching transition of a first switch of said half bridge using current mirror to provide a mirrored gate current signal, transferring said mirrored gate current signal through a galvanic insulation circuit, conditioning said mirrored gate current signal to create a gate pull-up command signal, combining said gate pull-up command signal with the gate command signal of a second switch of said half bridge in order to provide an advanced off to on transition of said second switch.

8 . The process according to claim 7 comprising resetting said gate pull-up command signal upon occurrence of gate activating pulses of said gate command signal.

Assignees

• Mitsubishi Electric Corp

Inventors

• Le Lesle Johan
• Lefevre Guillaume

Classifications

• H02M1/08

  Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters · CPC title

• H02M1/0048

  Circuits or arrangements for reducing losses (using snubbers H02M1/34) · CPC title

• H03K17/691

  using transformer coupling · CPC title

• H03K2217/0072

  Low side switches, i.e. the lower potential [DC] or neutral wire [AC] being directly connected to the switch and not via the load · CPC title

• H03K2217/0063

  High side switches, i.e. the higher potential [DC] or life wire [AC] being directly connected to the switch and not via the load · CPC title